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this is information on a product in full production. july 2012 doc id 14952 rev 6 1/89 1 stm8af6x26/4x/66/68 automotive 8-bit mcu, with up to 32 kbytes flash, data eeprom, 10-bit adc, timers, lin, spi, i2c, 3 to 5.5 v datasheet ? production data features core ?max f cpu : 16 mhz ? advanced stm8a core with harvard architecture and 3-stage pipeline ? average 1.6 cycles/instruction resulting in 10 mips at 16 mhz f cpu for industry standard benchmark memories ? flash program memory: 16 to 32 kbytes flash; data retention 20 years at 55 c after 1 kcycle ? data memory: 0.5 to 1 kbyte true data eeprom; endurance 300 kcycles ? ram: 1 to 2 kbytes clock management ? low-power crystal re sonator oscillator with external clock input ? internal, user-trimmable 16 mhz rc and low-power 128 khz rc oscillators ? clock security system with clock monitor reset and supply management ? wait/auto-wakeup/halt low-power modes with user definable clock gating ? low consumption power-on and power- down reset interrupt management ? nested interrupt controller with 32 vectors ? up to 34 external interrupts on 5 vectors timers ? up to 2 general purpose 16-bit pwm timers with up to 3 capcom channels each (ic, oc or pwm) ? advanced control timer: 16-bit, 4 capcom channels, 3 complementary outputs, dead- time insertion and flexible synchronization ? 8-bit ar basic timer with 8-bit prescaler ? auto-wakeup timer ? window and independent watchdog timers communication interfaces ?linuart ? lin 2.1 compliant, master/slave modes with automatic resynchronization ? spi interface up to 10 mbit/s or f master /2 ?i 2 c interface up to 400 kbit/s analog-to-digital converter (adc) ? 10-bit accuracy, 2lsb tue accuracy, 2lsb tue linearity adc and up to 10 multiplexed channels with individual data buffer ? analog watchdog, scan and continuous sampling mode i/os ? up to 38 user pins including 10 hs i/os ? highly robust i/o design, immune against current injection operating temperature up to 150 c qualification conforms to aec-q100 rev g table 1. device summary (1) 1. in the order code, ?f? applies to devices with flash program memory and data eeprom while ?h? refers to devices with flash program memory only. ?f? is replaced by ?p? for devices with fastrom (see tables 2 and 3 , and figure 47 ). part numbers: stm8af622x/4x stm8af6266/68 stm8af6268, stm8af6248, stm8af6266, stm8af6246, stm8af6226 part numbers: stm8af612x/4x (2) stm8af6166/68 (2) 2. not recommended for new design. stm8af6168, stm8af6148, stm8af6166, STM8AF6146, stm8af6126 lqfp48 7x7 lqfp32 7x7 vfqfpn32 5x5 www.st.com
contents stm8af61xx, stm8af62xx 2/89 doc id 14952 rev 6 contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 product line-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5 product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.1 stm8a central processing unit (cpu) . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.1.1 architecture and registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.1.2 addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.1.3 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.2 single wire interface module (swim) and debug module (dm) . . . . . . . . 13 5.2.1 swim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.2.2 debug module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.3 interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.4 flash program and data eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.4.1 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.4.2 write protection (wp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.4.3 protection of user boot code (ubc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.4.4 read-out protection (rop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.5 clock controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.5.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.5.2 16 mhz high-speed internal rc oscillator (hsi) . . . . . . . . . . . . . . . . . . 15 5.5.3 128 khz low-speed internal rc oscillator (lsi) . . . . . . . . . . . . . . . . . . . 16 5.5.4 16 mhz high-speed external crystal oscillator (hse) . . . . . . . . . . . . . . 16 5.5.5 external clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.5.6 clock security system (css) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.6 low-power operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.7 timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.7.1 watchdog timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.7.2 auto-wakeup counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.7.3 beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
stm8af61xx, stm8af62xx contents doc id 14952 rev 6 3/89 5.7.4 advanced control and general purpose timers . . . . . . . . . . . . . . . . . . . 18 5.7.5 basic timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.8 analog-to-digital converter (adc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.9 communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.9.1 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.9.2 inter integrated circuit (i 2 c) interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.9.3 universal asynchronous receiver/transmitter with lin support (linuart) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.10 input/output specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6 pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.1 package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.2 alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7 memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.2 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8 interrupt table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 9 option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 10 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 10.1 parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 10.1.1 minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 10.1.2 typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 10.1.3 typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 10.1.4 loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 10.1.5 pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 10.3.1 vcap external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 10.3.2 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 10.3.3 external clock sources and timing characteristics . . . . . . . . . . . . . . . . . 54 10.3.4 internal clock sources and timing characteristics . . . . . . . . . . . . . . . . . 56 10.3.5 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 10.3.6 i/o port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
contents stm8af61xx, stm8af62xx 4/89 doc id 14952 rev 6 10.3.7 reset pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 10.3.8 tim 1, 2, 3, and 4 timer specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 65 10.3.9 spi serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 10.3.10 i 2 c interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 10.3.11 10-bit adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 10.3.12 emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 10.4 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 10.4.1 reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 10.4.2 selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . . 74 11 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 11.1 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 12 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 13 stm8 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 13.1 emulation and in-circuit debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . 82 13.1.1 stice key features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 13.2 software tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 13.2.1 stm8 toolset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 13.2.2 c and assembly toolchains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 13.3 programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 14 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
stm8af61xx, stm8af62xx list of tables doc id 14952 rev 6 5/89 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. stm8af62xx product line-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 3. stm8af/h61xx product line-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 4. peripheral clock gating bit assignments in clk_ pckenr1/2 registers . . . . . . . . . . . . . . . 16 table 5. advanced control and general purpose timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 6. tim4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 7. adc naming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 8. communication peripheral naming correspondence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 9. legend/abbreviation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 10. stm8af61xx/62xx (32 kbytes) microcontroller pin description . . . . . . . . . . . . . . . . . . . . . 26 table 11. memory model for the devices covered in this datasheet. . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 12. i/o port hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 13. general hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 14. cpu/swim/debug module/interrupt controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 15. temporary memory unprotection registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 16. stm8a interrupt table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 17. option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 18. option byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 19. voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 20. current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 21. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 22. operating lifetime . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 23. general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 24. operating conditions at power-up/power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 25. total current consumption in run, wait and slow mode. general conditions for v dd apply, t a = -40 to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 26. total current consumption in halt and active-halt modes. general conditions for v dd apply, t a = -40 to 55 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 27. oscillator current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 28. programming current consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 table 29. typical peripheral current consumption v dd = 5.0 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 30. hse user external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 table 31. hse oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 32. hsi oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 33. lsi oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 34. flash program memory/data eeprom memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 35. flash program memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 36. data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 37. i/o static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 38. nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 39. tim 1, 2, 3, and 4 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 40. spi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 41. i 2 c characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 42. adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 43. adc accuracy for v dda = 5 v. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 44. ems data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 45. emi data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 46. esd absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
list of tables stm8af61xx, stm8af62xx 6/89 doc id 14952 rev 6 table 47. electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 48. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 49. vfqfpn 32-lead very thin fine pitch quad flat no-lead package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 50. lqfp 48-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . 77 table 51. lqfp 32-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . 79 table 52. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
stm8af61xx, stm8af62xx list of figures doc id 14952 rev 6 7/89 list of figures figure 1. stm8a block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 2. flash memory organization of stm8a products. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 3. vfqfpn/lqfp 32-pin pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 4. lqfp 48-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 5. register and memory map of stm8a products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 6. pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 7. pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 8. f cpumax versus v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 9. external capacitor c ext . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 10. typ. i dd(run)hse vs. v dd @f cpu = 16 mhz, peripheral = on . . . . . . . . . . . . . . . . . . . . . . . 53 figure 11. typ. i dd(run)hse vs. f cpu @ v dd = 5.0 v, peripheral = on . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 12. typ. i dd(run)hsi vs. v dd @ f cpu = 16 mhz, peripheral = off . . . . . . . . . . . . . . . . . . . . . . . 54 figure 13. typ. i dd(wfi)hse vs. v dd @ f cpu = 16 mhz, peripheral = on . . . . . . . . . . . . . . . . . . . . . . . 54 figure 14. typ. i dd(wfi)hse vs. f cpu @ v dd = 5.0 v, peripheral = on . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 15. typ. i dd(wfi)hsi vs. v dd @ f cpu = 16 mhz, peripheral = off . . . . . . . . . . . . . . . . . . . . . . . 54 figure 16. hse external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 17. hse oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 18. typical hsi frequency vs v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 19. typical lsi frequency vs v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 20. typical v il and v ih vs v dd @ four temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 21. typical pull-up resistance r pu vs v dd @ four temperatures . . . . . . . . . . . . . . . . . . . . . . . 60 figure 22. typical pull-up current i pu vs v dd @ four temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 23. typ. v ol @ v dd = 3.3 v (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 24. typ. v ol @ v dd = 5.0 v (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 25. typ. v ol @ v dd = 3.3 v (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 26. typ. v ol @ v dd = 5.0 v (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 27. typ. v ol @ v dd = 3.3 v (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 28. typ. v ol @ v dd = 5.0 v (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 29. typ. v dd - v oh @ v dd = 3.3 v (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 30. typ. v dd - v oh @ v dd = 5.0 v (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 31. typ. v dd - v oh @ v dd = 3.3 v (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 32. typ. v dd - v oh @ v dd = 5.0 v (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 33. typical nrst v il and v ih vs v dd @ four temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 34. typical nrst pull-up resistance r pu vs v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 35. typical nrst pull-up current i pu vs v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 36. recommended reset pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 37. spi timing diagram where slave mode and cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 38. spi timing diagram where slave mode and cpha = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 39. spi timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 figure 40. typical application with adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 figure 41. adc accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 figure 42. vfqfpn 32-lead very thin fine pitch quad flat no-lead package (5 x 5). . . . . . . . . . . . . . . 76 figure 43. lqfp 48-pin low profile quad flat package (7 x 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 figure 44. lqfp 48-pin recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 figure 45. lqfp 32-pin low profile quad flat package (7 x 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 figure 46. lqfp 32-pin recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 figure 47. ordering information scheme (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
introduction stm8af61xx, stm8af62xx 8/89 doc id 14952 rev 6 1 introduction this datasheet refers to the stm8af61xx (stm8af612x, stm8af614x, stm8af6166, and stm8af6168) and stm8af62xx products with 16 to 32 kbytes of flash program memory. in the order code, the letter ?f? refers to product versions with data eeprom and ?h? refers to product versions without data eeprom. the iden tifiers ?f? and ?h? do not coexist in a given order code. the datasheet contains the description of family features, pinout, electrical characteristics, mechanical data and ordering information. for complete information on the stm8a microcontroller memory, registers and peripherals, please refer to stm8s and stm8a microcon troller families reference manual (rm0016). for information on programming, erasing and protection of the internal flash memory please refer to the stm8 flash programming manual (pm0051). for information on the debug and swim (single wire interface module) refer to the stm8 swim communication protocol and debug module user manual (um0470). for information on the stm8 core, please refer to the stm8 cpu programming manual (pm0044).
stm8af61xx, stm8af 62xx description doc id 14952 rev 6 9/89 2 description the stm8af61xx and stm8af62xx automotive 8-bit microcontrollers offer from 16 to 32 kbytes of flash program memory and integrat ed true data eeprom. th ey are referred to as medium density stm8a devices in the stm8s and stm8a micr ocontroller families reference manual (rm0016). all devices of the stm8a product line provide the following benefits: reduced system cost, performance and robustness, short development cycles, and product longevity. the system cost is reduced thanks to an integrated true data eeprom for up to 300 k write/erase cycles and a high system integration level with internal clock oscillators, watchdog, and brown-out reset. device performance is ensured by a clock frequency of up to 16 mhz cpu and enhanced characteristics which include robust i/o, independent watchdogs (with a separate clock source), and a clock security system. short development cycles are g uaranteed due to app lication scalability across a common family product architecture with compatible pinout, memory map and and modular peripherals. full documentation is offered with a wide choice of development tools. product longevity is ensured in the stm8a fam ily thanks to their advanced core which is made in a state-of-the art technology for automotive applications with 3.3 v to 5 v operating supply. all stm8a and st7 microcontrollers are supported by the same tools including stvd/stvp development environment, the stice emulator and a low-cost, third party in- circuit debugging tool.
product line-up stm8af61xx, stm8af62xx 10/89 doc id 14952 rev 6 3 product line-up 2 2 table 2. stm8af62xx product line-up order code package medium density flash program memory (bytes) ram (bytes) data ee (bytes) 10-bit a/d ch. timers (ic/oc/pwm) serial interfaces i/0 wakeup pins stm8af/p6268 lqfp48 (7x7) 32 k 2 k 1 k 10 1x8-bit: tim4 3x16-bit: tim1, tim2, tim3 (9/9/9) lin(uart), spi, i2c 38/35 stm8af/p6248 16 k 2 k 0.5 k stm8af/p6266 lqfp32 (7x7) 32 k 2 k 1 k 7 1x8-bit: tim4 3x16-bit: tim1, tim2, tim3 (8/8/8) lin(uart), spi, i2c 25/23 stm8af/p6246 16 k 2 k 0.5 k stm8af/p6226 8 k 2 k 384 stm8af/p6266 vfqfpn32 32 k 2 k 1 k 7 1x8-bit: tim4 3x16-bit: tim1, tim2, tim3 (8/8/8) lin(uart), spi, i2c 25/23 stm8af/p6246 16 k 2 k 0.5 k table 3. stm8af/h61xx product line-up (1) 1. these devices are not recommended for new design. order code package medium density flash program memory (bytes) ram (bytes) data ee (bytes) 10-bit a/d ch. timers (ic/oc/pwm) serial interfaces i/0 wakeup pins stm8af/h/p6168 lqfp48 (7x7) 32 k 2 k 1 k 10 1x8-bit: tim4 3x16-bit: tim1, tim2, tim3 (9/9/9) lin(uart), spi, i2c 38/35 stm8af/h/p6148 16 k 1 k 0.5 k stm8af/h/p6166 lqfp32 (7x7) 32 k 2 k 1 k 7 1x8-bit: tim4 3x16-bit: tim1, tim2, tim3 (8/8/8) lin(uart), spi, i2c 25/23 stm8af/h/p6146 16 k 1 k 0.5 k stm8af/h/p6126 8 k 512 384
stm8af61xx, stm8af62xx block diagram doc id 14952 rev 6 11/89 4 block diagram figure 1. stm8a block diagram 1. legend: adc: analog-to-digital converter becan: controller area network bor: brownout reset i2c: inter-integrated circuit multimaster interface iwdg: independent window watchdog linuart: local interconnect network unive rsal asynchronous receiver transmitter por: power on reset spi: serial peripheral interface swim: single wire interface module usart: universal synchronous as ynchronous receiver transmitter window wdg: window watchdog xtal 1 - 16 mhz rc int. 16 mhz rc int. 128 khz stm8a core debug/swim i 2 c spi linuart 16-bit general purpose awu timer reset block reset clock controller detector clock to peripherals and core 10 mbit/s 16 channels window wdg iwdg up to 32 kbytes up to 1 kbytes up to 2 kbytes boot rom 10-bit adc 9 capcom reset 400 kbit/s master/slave single wire automatic debug interf. channels program flash 16-bit advanced control timer (tim1) 8-bit basic timer (tim4) data eeprom ram up to address and data bus resynchronization timers (tim2, tim3) por bor
product overview stm8af61xx, stm8af62xx 12/89 doc id 14952 rev 6 5 product overview this section is intended to describe the family features that are actually implemented in the products covered by this datasheet. for more detailed information on each feature please refer to the stm8s and stm8a microcontroller families re ference manual (rm0016). 5.1 stm8a central processing unit (cpu) the 8-bit stm8a core is a modern cisc core and has been designed for code efficiency and performance. it contains 21 internal regist ers (six directly addressable in each execution context), 20 addressing modes including indexed indirect and relative addressing and 80 instructions. 5.1.1 architecture and registers harvard architecture 3-stage pipeline 32-bit wide program memory bus with single cycle fetching for most instructions x and y 16-bit index registers, enabling indexed addressing modes with or without offset and read-modify-write type data manipulations 8-bit accumulator 24-bit program counter with 16-mbyte linear memory space 16-bit stack pointer with access to a 64 kbyte stack 8-bit condition code register with seven condition flags for the result of the last instruction. 5.1.2 addressing 20 addressing modes indexed indirect addressing mode for look-up tables located anywhere in the address space stack pointer relative addressing mode for efficient implementation of local variables and parameter passing 5.1.3 instruction set 80 instructions with 2-byte average instruction size standard data movement and logic/arithmetic functions 8-bit by 8-bit multiplication 16-bit by 8-bit and 16-bit by 16-bit division bit manipulation data transfer between stack and accumulator (push/pop) with direct stack access data transfer using the x and y registers or direct memory-to-memory transfers
stm8af61xx, stm8af62xx product overview doc id 14952 rev 6 13/89 5.2 single wire interface module (swim) and debug module (dm) 5.2.1 swim the single wire interface module, swim, together with an integrated debug module, permits non-intrusive, real-time in-circuit debugging and fast memory programming. the interface can be activated in all device operation modes and can be connected to a running device (hot plugging).the maximum data transmission speed is 145 bytes/ms. 5.2.2 debug module the non-intrusive debugging module features a performance close to a full-flavored emulator. besides memory and peripheral operation, cpu operation can also be monitored in real-time by means of shadow registers. r/w of ram and peripheral registers in real-time r/w for all resources when th e application is stopped breakpoints on all program-memory instructions (software breakpoints), except the interrupt vector table two advanced breakpoints and 23 predefined breakpoint configurations 5.3 interrupt controller nested interrupts with three software priority levels 21 interrupt vectors with hardware priority five vectors for external interrupts (up to 34 depending on the package) trap and reset interrupts 5.4 flash program and data eeprom 8 kbytes to 32 kbytes of medium density single voltage program flash memory up to 1 kbytes true (n ot emulated) data eeprom read while write: writing in the data memory is possible while executing code in the flash program memory the whole flash program memo ry and data eeprom are fact ory programmed with 0x00. 5.4.1 architecture the memory is organized in blocks of 128 bytes each read granularity: 1 word = 4 bytes write/erase granularity: 1 word (4 bytes) or 1 block (128 bytes) in parallel writing, erasing, word and block management is handled automatically by the memory interface.
product overview stm8af61xx, stm8af62xx 14/89 doc id 14952 rev 6 5.4.2 write protection (wp) write protection in application mode is intended to avoid unintentional overwriting of the memory. the write protection can be removed temporarily by executing a specific sequence in the user software. 5.4.3 protection of user boot code (ubc) if the user chooses to update the flash program memory using a specific boot code to perform in application programming (iap), this boot code needs to be protected against unwanted modification. in the stm8a a memory area of up to 32 kbytes can be protected from overwriting at user option level. other than the standard write protection, the ubc protection can exclusively be modified via the debug interface, the user software cannot modify the ubc protection status. the ubc memory area contains the reset and interrupt vectors and its size can be adjusted in increments of 512 bytes by programming the ubc and nubc option bytes (see section 9: option bytes on page 41 ). figure 2. flash memory organization of stm8a products 5.4.4 read-out protection (rop) the stm8a provides a read-out protection of the code and data memory which can be activated by an option byte setting (see the rop option byte in section 10). the read-out protection prevents reading and writing flash program memory, data memory and option bytes via the debug module and swim interface. this protection is active in all device operation modes. any attempt to remove the protection by overwriting the rop option byte triggers a global erase of the program and data memory. the rop circuit may provide a temporary access for debugging or failure analysis. the temporary read access is protected by a user defined, 8-byte keyword stored in the option byte area. this keyword must be entered via the swim interface to temporarily unlock the device. programmable area data ubc area flash program memory area data memory area (1 kbytes) eeprom remains write protected during iap memory write access possible for iap option bytes flash program memory maximum 32 kbytes
stm8af61xx, stm8af62xx product overview doc id 14952 rev 6 15/89 if desired, the temporary unlock mechanism can be permanently disabled by the user through opt6/nopt6 option bytes. 5.5 clock controller the clock controller distributes the system clock coming from different o scillators to the core and the peripherals. it also manages clock gating for low-power modes and ensures clock robustness. 5.5.1 features clock sources: ? 16 mhz high-speed internal rc oscillator (hsi) ? 128 khz low-speed internal rc (lsi) ? 1-16 mhz high-speed external crystal (hse) ? up to 16 mhz high-speed user-external clock (hse user-ext) reset : after reset the microcontroller restarts by default with an internal 2-mhz clock (16 mhz/8). the clock source and speed can be changed by the application program as soon as the code execution starts. safe clock switching : clock sources can be changed safely on the fly in run mode through a configuration register. the clock signal is not switched until the new clock source is ready. the design guarantees glitch-free switching. clock management : to reduce power consumption, the clock controller can stop the clock to the core or individual peripherals. wakeup : in case the device wakes up from low-power modes, the internal rc oscillator (16 mhz/8) is used for quick star tup. after a stabilization time, the device switches to the clock source that was selected before halt mode was entered. clock security system (css) : the css permits monitoring of external clock sources and automatic switching to the internal rc (16 mhz/8) in case of a clock failure. configurable main clock output (cco) : this feature permits to outputs a clock signal for use by the application. 5.5.2 16 mhz high-speed inter nal rc oscillator (hsi) default clock after reset 2 mhz (16 mhz/8) fast wakeup time user trimming the register clk_hsitrimr with three trimming bits plus one additional bit for the sign permits frequency tuning by the application program. the adjustment range covers all possible frequency variations versus supply voltage and temperature. this trimming does not change the initial production setting. for reason of compatibility with other devices from the stm8a family, a special mode with only two trimming bits plus sign can be selected. this selection is controlled with the hsitrim0 bit in the option byte registers opt3 and nopt3.
product overview stm8af61xx, stm8af62xx 16/89 doc id 14952 rev 6 5.5.3 128 khz low-speed inter nal rc oscillator (lsi) the frequency of this clock is 128 khz and it is independent from the main clock. it drives the independent watchdog or the awu wakeup timer. in systems which do not need independent clock sources for the watchdog counters, the 128 khz signal can be used as the system clock. this configuration has to be enabled by setting an option byte (opt3/opt3n, bit lsi_en). 5.5.4 16 mhz high-speed external crystal oscillator (hse) the external high-speed crystal oscillator ca n be selected to deliver the main clock in normal run mode. it operates with quartz crystals and ceramic resonators. frequency range: 1 mhz to 16 mhz crystal oscillation mode : preferred fundamental i/os: standard i/o pins multiplexed with oscin, oscout 5.5.5 external clock input an external clock signal can be applied to th e oscin input pin of the crystal oscillator. the frequency range is 0 to 16 mhz. 5.5.6 clock securit y system (css) the clock security system protects against a syste m stall in case of an external crystal clock failure. in case of a clock failure an interrupt is generated and the high-speed internal clock (hsi) is automatically selected with a frequency of 2 mhz (16 mhz/8). table 4. peripheral clock gating bit assignments in clk_pckenr1/2 registers bit peripheral clock bit peripheral clock bit peripheral clock bit peripheral clock pcken17 tim1 pcken13 linuart pcken27 reserved pcken23 adc pcken16 tim3 pcken12 reserved pcken26 reserved pcken22 awu pcken15 tim2 pcken11 spi pcken25 reserved pcken21 reserved pcken14 tim4 pcken10 i 2 c pcken24 reserved pcken20 reserved
stm8af61xx, stm8af62xx product overview doc id 14952 rev 6 17/89 5.6 low-power operating modes for efficient power management, the application can be put in one of four different low power modes. you can configure each mode to obtain the best compromise between lowest power consumption, fastest start-up time and available wakeup sources. wait mode in this mode, the cpu is stopped but peripherals are kept running. the wakeup is performed by an internal or external interrupt or reset. active-halt mode with regulator on in this mode, the cpu and peripheral clocks are stopped. an internal wakeup is generated at programmable intervals by the auto wake up unit (awu). the main voltage regulator is kept powered on, so curr ent consumption is higher than in active- halt mode with regulator off, but the wakeup time is faster. wakeup is triggered by the internal awu interrupt, external interrupt or reset. active-halt mode with regulator off this mode is the same as active-halt with regulator on, except that the main voltage regulator is powered off, so the wake up time is slower. halt mode cpu and peripheral clocks are stopped, the main voltage regulator is powered off. wakeup is triggered by external event or reset. in all modes the cpu and peripherals remain permanently powered on, the system clock is applied only to selected modules. the ram content is preserved and the brown-out reset circuit remains activated. 5.7 timers 5.7.1 watchdog timers the watchdog system is based on two independent timers providing maximum security to the applications. the watchdog timer activity is controlled by the application program or option bytes. once the watchdog is activated, it cannot be disabled by the user program without going through reset. window watchdog timer the window watchdog is used to detect the occurrence of a software fault, usually generated by external interferences or by unexpected logical conditions, which cause the application program to abandon its normal sequence. the window function can be used to trim the watchdog behavior to match the application timing perfectly. the application software must refresh the counter before time-out and during a limited time window. if the counter is refreshed outside this time window, a reset is issued.
product overview stm8af61xx, stm8af62xx 18/89 doc id 14952 rev 6 independent watchdog timer the independent watchdog peripheral can be used to resolve malfunctions due to hardware or software failures. it is clocked by the 128 khz lsi internal rc clock source, and thus stays active even in case of a cpu clock failure. if the hardware watchdog feature is enabled through the device option bits, the watchdog is automatically enabled at power-on, and generates a reset unless the key register is written by software before the counter reaches the end of count. 5.7.2 auto-wakeup counter this counter is used to cyclica lly wakeup the device in active-halt mode. it can be clocked by the internal 128 khz internal low-freq uency rc oscillator or external clock. lsi clock can be internally connected to tim3 input capture channel 1 for calibration. 5.7.3 beeper this function generates a rectangular signal in the range of 1, 2 or 4 khz which can be output on a pin. this is useful when audible sounds without interference need to be generated for use in the application. 5.7.4 advanced control and g eneral purpose timers stm8a devices described in this datasheet, contain up to three 16-bit advanced control and general purpose timers providing nine capcom channels in total. a capcom channel can be used either as input compare, output compare or pwm channel. these timers are named tim1, tim2 and tim3. table 5. advanced control and general purpose timers timer counter width counter type prescaler factor channels inverted outputs repetition counter trigger unit external trigger break input tim1 16-bit up/down 1 to 65536 4 3 yes yes yes yes tim2 16-bit up 2 n n = 0 to 15 3 none no no no no tim3 16-bit up 2 n n = 0 to 15 2 none no no no no
stm8af61xx, stm8af62xx product overview doc id 14952 rev 6 19/89 tim1: advanced control timer this is a high-end timer designed for a wide range of control applications. with its complementary outputs, dead-ti me control and center-aligned pwm capability, the field of applications is extended to motor control, lighting and bridge driver. 16-bit up, down and up/down ar (auto-reload) counter with 16-bit fractional prescaler. four independent capcom channels configurable as input capture, output compare, pwm generation (edge and center aligned mode) and single pulse mode output trigger module which allows the interaction of tim1 with other on-chip peripherals. in the present implementation it is possible to trigger the adc upon a timer event. external trigger to change the timer behavior depending on external signals break input to force the timer outputs into a defined state three complementary outputs with adjustable dead time interrupt sources: 4 x input capture/output compare, 1 x overflow/update, 1 x break tim2 and tim3: 16-bit general purpose timers 16-bit auto-reload up-counter 15-bit prescaler adjustable to fixed power of two ratios 1?32768 timers with three or two individually configurable capcom channels interrupt sources: 2 or 3 x input capture/output compare, 1 x overflow/update 5.7.5 basic timer the typical usage of this timer (tim4) is the generation of a clock tick. 8-bit auto-reload, adjustable prescaler ratio to any power of two from 1 to 128 clock source: master clock interrupt source: 1 x overflow/update table 6. tim4 timer counter width counter type prescaler factor channels inverted outputs repetition counter trigger unit external trigger break input tim4 8-bit up 2 n n = 0 to 7 0 none no no no no
product overview stm8af61xx, stm8af62xx 20/89 doc id 14952 rev 6 5.8 analog-to-digital converter (adc) the stm8a products described in this datasheet contain a 10-bit successive approximation adc with up to 16 multiplexed input channels, depending on the package. the adc name differs between the datasheet and the stm8a/s reference manual (see ta bl e 7 ). adc features 10-bit resolution single and continuous conversion modes programmable prescaler: f master divided by 2 to 18 conversion trigger on timer events and external events interrupt generation at end of conversion selectable alignment of 10-bit data in 2 x 8 bit result register shadow registers for data consistency adc input range: v ssa v in v dda analog watchdog schmitt-trigger on analog inputs can be disabled to reduce power consumption scan mode (single and continuous) dedicated result register for each conversion channel buffer mode for continuous conversion note: an additional ain12 analog input is not selectable in adc scan mode or with analog watchdog. values converted from ain12 are stored only into the adc_drh/adc_drl registers. 5.9 communication interfaces the following sections give a brief overview of the communication peripheral. some peripheral names differ between the datasheet and the stm8a/s reference manual (see ta bl e 8 ). table 7. adc naming peripheral name in datasheet peripheral name in reference manual (rm0016) adc adc1 table 8. communication peripheral naming correspondence peripheral name in datasheet peripheral name in reference manual (rm0016) linuart uart2
stm8af61xx, stm8af62xx product overview doc id 14952 rev 6 21/89 5.9.1 serial peripheral interface (spi) the devices covered by this datasheet contain one spi. the spi is available on all the supported packages. maximum speed: 10 mbit/s or f master /2 both for master and slave full duplex synchronous transfers simplex synchronous transfers on two lines with a possible bidirectional data line master or slave operation - selectable by hardware or software crc calculation 1 byte tx and rx buffer slave mode/master mode management by hardware or software for both master and slave programmable clock polarity and phase programmable data order with msb-first or lsb-first shifting dedicated transmission a nd reception flags with interrupt capability spi bus busy status flag hardware crc feature for reliable communication: ? crc value can be transmitted as last byte in tx mode ? crc error checking for last received byte 5.9.2 inter integrated circuit (i 2 c) interface the devices covered by this datasheet contain one i 2 c interface. the inte rface is available on all the supported packages. i 2 c master features: ? clock generation ? start and stop generation i 2 c slave features: ? programmable i 2 c address detection ? stop bit detection generation and detection of 7-bit/10-bit addressing and general call supports different communication speeds: ? standard speed (up to 100 khz), ? fast speed (up to 400 khz) status flags: ? transmitter/receiver mode flag ? end-of-byte transmission flag ?i 2 c busy flag error flags: ? arbitration lost condition for master mode ? acknowledgement failure after address/data transmission ? detection of misplaced start or stop condition ? overrun/underrun if clock stretching is disabled
product overview stm8af61xx, stm8af62xx 22/89 doc id 14952 rev 6 interrupt: ? successful address/data communication ? error condition ? wakeup from halt wakeup from halt on address detection in slave mode 5.9.3 universal asynchronous recei ver/transmitter with lin support (linuart) the devices covered by this datasheet contain one linuart interface. the interface is available on all the supported packages. the linuart is an asynchronous serial communication interface which supports extensive lin functions tailored for lin slave applications. in lin mode it is compliant to the lin standards rev 1.2 to rev 2.1. detailed feature list: lin mode master mode: lin break and delimiter generation lin break and delimiter detection with separate flag and interrupt source for read back checking. slave mode: autonomous header handling ? one single interrupt per valid header mute mode to filter responses identifier parity error checking lin automatic resynchronizat ion, allowing operat ion with internal rc oscillator (hsi) clock source break detection at any time, even during a byte reception header errors detection: ? delimiter too short ? synch field error ? deviation error (if automatic resynchronization is enabled) ? framing error in synch field or identifier field ? header time-out
stm8af61xx, stm8af62xx product overview doc id 14952 rev 6 23/89 uart mode full duplex, asynchronous communications - nrz standard format (mark/space) high-precision baud rate generator ? a common programmable transmit and receive baud rates up to f master /16 programmable data word length (8 or 9 bits) ? 1 or 2 stop bits ? parity control separate enable bits for transmitter and receiver error detection flags reduced power consumption mode multi-processor communication - enter mute mode if address match does not occur wakeup from mute mode (by idle line detection or address mark detection) two receiver wakeup modes: ? address bit (msb) ? idle line 5.10 input/output specifications the product features four different i/o types: standard i/o 2 mhz fast i/o up to 10 mhz high sink 8 ma, 2 mhz true open drain (i 2 c interface) to decrease emi (electromagnetic interference), high sink i/os have a limited maximum slew rate. the rise and fall times are similar to those of standard i/os. the analog inputs are equipped with a low leakage analog switch. additionally, the schmitt- trigger input stage on the analog i/os can be disabled in order to reduce the device standby consumption. stm8a i/os are designed to withstand current injection. for a negative injection current of 4 ma, the resulting leakage current in the adjacent input does not exceed 1 a. thanks to this feature, external protection diodes against current injection are no longer required.
pinouts and pin description stm8af61xx, stm8af62xx 24/89 doc id 14952 rev 6 6 pinouts and pin description 6.1 package pinouts figure 3. vfqfpn/lqfp 32-pin pinout 1. (hs) high sink capability. i2c_scl/ain4/pb4 tim1_etr/ain3/pb3 tim1_ch3n/ain2/pb2 tim1_ch2n/ain1/pb1 tim1_ch1n/ain0/pb0 v dda v ssa i2c_sda/ain5/pb5 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 9 101112131415 16 1 2 3 4 5 6 7 8 vcap v dd v ddio ain12/pf4 nrst oscin/pa1 oscout/pa2 v ss pc3 (hs)/tim1_ch3 pc2 (hs)/tim1_ch2 pc1 (hs)/tim1_ch1 pe5/spi_nss pc7/spi_miso pc6/spi_mosi pc5/spi_sck pc4 (hs)/tim1_ch4 pd3 (hs)/tim2_ch2/adc_etr pd2 (hs)/tim3_ch1/tim2_ch3 pd1 (hs)/swim pd0 (hs)/tim3_ch2/clk_cco/tim1_brk pd7/tli pd6/linuart_rx pd5/linuart_tx pd4 (hs)/tim2_ch1/beep
stm8af61xx, stm8af62xx pinouts and pin description doc id 14952 rev 6 25/89 figure 4. lqfp 48-pin pinout 2. (hs) high sink capability. table 9. legend/abbreviation type i= input, o = output, s = power supply level input cm = cmos (standard for all i/os) output hs = high sink (8 ma) output speed o1 = standard (up to 2 mhz) o2 = fast (up to 10 mhz) o3 = fast/slow programmability with slow as default state after reset o4 = fast/slow programmability with fast as default state after reset port and control configuration input float = floating, wpu = weak pull-up output t = true open drain, od = open drain, pp = push pull reset state bold x (pin state a fter reset release). unless otherwise specified, the pin state is the same during the reset phase (i.e. ?under reset?) and after internal reset release (i.e. at reset state). 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 48 47 46 45 pa6 ain8/pe7 pc1 (hs)/tim1_ch1 pe5/spi_nss pg1 ain9/pe6 pd3 (hs)/tim2_ch2/adc_etr pd2 (hs)/tim3_ch1 pe0/clk_cco pe1/i 2 c_scl pe2/i 2 c_sda pe3/tim1_bkin pd7/tli pd6/linuart_rx pd5/linuart_tx pd4 (hs)/tim2_ch1/beep pd1 (hs)/swim pd0 (hs)/tim3_ch2 v ssio_2 pc5/spi_sck pc4 (hs)/tim1_ch4 pc3 (hs)/tim1_ch3 p c2 (hs)/tim1_ch2 pg0 pc7/spi_miso pc6/spi_mosi v ddio_2 ain7/pb7 ain6/pb6 ain5/pb5 ain4/pb4 tim1_etr/ain3/pb3 tim1_ch3n/ain2/pb2 tim1_ch2n/ain1/pb1 tim1_ch1n/ain0/pb0 v dda v ssa v ss vcap v dd v ddio_1 tim2_ch3/pa3 pa4 pa5 nrst oscin/pa1 oscout/pa2 v ssio_1
pinouts and pin description stm8af61xx, stm8af62xx 26/89 doc id 14952 rev 6 table 10. stm8af61xx/62xx (32 kbytes) microcontroller pin description (1)(2) pin number pin name type input output main function (after reset) default alternate function alternate function after remap [option bit] lqfp48 vfqfpn/lqfp32 floating wpu ext. interrupt high sink speed od pp 1 1 nrst i/o - x - - - - - reset ? 22pa1/oscin (3) i/o x x- -o1xx port a1 resonator/crystal in ? 3 3 pa2/oscout i/o x xx -o1xx port a2 resonator/crystal out ? 4-v ssio_1 s - - - - - - - i/o ground ? 54v ss s - - - - - - - digital ground ? 6 5 vcap s - - - - - - - 1.8 v regulator capacitor ? 76v dd s - - - - - - - digital power supply ? 87v ddio_1 s - - - - - - - i/o power supply ? - 8 pf4/ain12 (4)(5) i/o x x-o1xx port f4 analog input 12 ? 9 - pa3/tim2_ch3 i/o x xx -o1xx port a3 timer 2 - channel 3 tim3_ch1 [afr1] 10 - pa4 i/o x xx -o3xx port a4 ? 11 - pa5 i/o x xx -o3xx port a5 ? 12 - pa6 i/o x xx -o3xx port a6 ? 13 9 v dda s - - - - - - - analog power supply ? 14 10 v ssa s - - - - - - - analog ground ? 15 - pb7/ain7 i/o x xx -o1xx port b7 analog input 7 ? 16 - pb6/ain6 i/o x xx -o1xx port b6 analog input 6 ? 17 11 pb5/ain5 i/o x xx -o1xx port b5 analog input 5 i 2 c_sda [afr6] 18 12 pb4/ain4 i/o x xx -o1xx port b4 analog input 4 i 2 c_scl [afr6] 19 13 pb3/ain3 i/o x xx -o1xx port b3 analog input 3 tim1_etr [afr5] 20 14 pb2/ain2 i/o x xx -o1xx port b2 analog input tim1_ ncc3 [afr5] 21 15 pb1/ain1 i/o x xx -o1xx port b1 analog input 1 tim1_ ncc2 [afr5] 22 16 pb0/ain0 i/o x xx -o1xx port b0 analog input 0 tim1_ ncc1 [afr5]
stm8af61xx, stm8af62xx pinouts and pin description doc id 14952 rev 6 27/89 23 - pe7/ain8 i/o x x-o1xx port e7 analog input 8 ? 24 pe6/ain9 i/o x xx -o1xx port e7 analog input 9 ? 25 17 pe5/spi_nss i/o x xx -o1xx port e5 spi master/slave select ? 26 18 pc1/tim1_ch1 i/o x xxhso3xx port c1 timer 1 - channel 1 ? 27 19 pc2/tim1_ch2 i/o x xxhso3xx port c2 timer 1- channel 2 ? 28 20 pc3/tim1_ch3 i/o x xxhso3xx port c3 timer 1 - channel 3 ? 29 21 pc4/tim1_ch4 i/o x xxhso3xx port c4 timer 1 - channel 4 ? 30 22 pc5/spi_sck i/o x xx o3xx port c5 spi clock ? 31 - v ssio_2 s - - - - - - - i/o ground ? 32 - v ddio_2 s - - - - - - - i/o power supply ? 33 23 pc6/spi_mosi i/o x xx -o3xx port c6 spi master out/ slave in ? 34 24 pc7/spi_miso i/o x xx -o3xx port c7 spi master in/ slave out ? 35 - pg0 i/o x x- -o1xx port g0 -? 36 - pg1 i/o x x- -o1xx port g1 -? 37 - pe3/tim1_bkin i/o x xx -o1xx port e3 timer 1 - break input ? 38 - pe2/i 2 c_sda i/o x -x-o1t (6) - port e2 i 2 c data ? 39 - pe1/i 2 c_scl i/o x -x-o1t (6) - port e1 i 2 c clock ? 40 - pe0/clk_cco i/o x xx -o3xx port e0 configurable clock output ? 41 25 pd0/tim3_ch2 i/o x xxhso3xx port d0 timer 3 - channel 2 tim1_bkin [afr3]/ clk_cco [afr2] 42 26 pd1/swim (7) i/o x x xhso4x x port d1 swim data interface ? 43 27 pd2/tim3_ch1 i/o x xxhso3xx port d2 timer 3 - channel 1 tim2_ch3 [afr1] 44 28 pd3/tim2_ch2 i/o x xxhso3xx port d3 timer 2 - channel 2 adc_etr [afr0] 45 29 pd4/tim2_ch1/ beep i/o x xxhso3xx port d4 timer 2 - channel 1 beep output [afr7] 46 30 pd5/ linuart_tx i/o x xx -o1xx port d5 linuart data transmit ? table 10. stm8af61xx/62xx (32 kbytes) microcontroller pin description (1)(2) (continued) pin number pin name type input output main function (after reset) default alternate function alternate function after remap [option bit] lqfp48 vfqfpn/lqfp32 floating wpu ext. interrupt high sink speed od pp
pinouts and pin description stm8af61xx, stm8af62xx 28/89 doc id 14952 rev 6 6.2 alternate function remapping as shown in the rightmost column of ta b l e 10 , some alternate functions can be remapped at different i/o ports by programming one of eight afr (alternate function remap) option bits. refer to section 9: option bytes on page 41 . when the remapping option is active, the default alternate function is no longer available. to use an alternate function, the corresponding pe ripheral must be enabled in the peripheral registers. alternate function remapping d oes not effect gpio capabilitie s of the i/o ports (see the gpio section of the stm8s and stm8a microcontroller families reference manual, rm0016). 47 31 pd6/ linuart_rx i/o x xx -o1xx port d6 linuart data receive ? 48 32 pd7/tli (8) i/o x xx -o1xx port d7 top level interrupt ? 1. refer to table 9 for the definition of the abbreviations. 2. reset state is shown in bold. 3. in halt/active-halt mode this pad behaves in the following way: - the input/output path is disabled - if the hse clock is used for wakeup, the internal weak pull up is disabled - if the hse clock is off, internal weak pull up setting from corr esponding or bit is used by managing the or bit correctly, it must be ensured that the pad is not left floati ng during halt/active-halt. 4. on this pin, a pull-up resistor as specified in table 37 . i/o static characteristics is enabled during the reset phase of the product. 5. ain12 is not selectable in adc scan mode or with analog watchdog. 6. in the open-drain output column, ?t? de fines a true open-drain i/o (p -buffer, week pull-up, and protection diode to v dd are not implemented) 7. the pd1 pin is in input pull-up duri ng the reset phase and after reset release. 8. if this pin is configured as interru pt pin, it will trigger the tli. table 10. stm8af61xx/62xx (32 kbytes) microcontroller pin description (1)(2) (continued) pin number pin name type input output main function (after reset) default alternate function alternate function after remap [option bit] lqfp48 vfqfpn/lqfp32 floating wpu ext. interrupt high sink speed od pp
stm8af61xx, stm8af62xx memory and register map doc id 14952 rev 6 29/89 7 memory and register map 7.1 memory map figure 5. register and memory map of stm8a products table 11. memory model for the devices covered in this datasheet flash program memory size flash program memory end address ram size ram end address stack roll-over address 32k 0x00 0ffff 2k 0x00 07ff 0x00 0600 16k 0x00 0bfff 8k 0x00 09fff up to 1 kbyte data eeprom hw registers cpu/swim/debug/itc registers it vectors up to 32 kbytes of 00 0000 ram end 00 4000 00 4800 00 5000 00 581d 00 6000 00 6800 00 7f00 00 8000 flash program memory end 00 8080 reserved reserved stack up to 2 kbytes ram 00 4400 reserved option bytes 00 4900 reserved 2 kbytes of boot rom flash program memory
memory and register map stm8af61xx, stm8af62xx 30/89 doc id 14952 rev 6 7.2 register map in this section the memory and register map of the devices covered by this datasheet is described. for a detailed description of the functionality of the registers, refer to the reference manual rm0016. table 12. i/o port hardware register map address block register label register name reset status 0x00 5000 port a pa_odr port a data output latch register 0x00 0x00 5001 pa_idr port a input pin value register 0xxx (1) 0x00 5002 pa_ddr port a data direction register 0x00 0x00 5003 pa_cr1 port a control register 1 0x00 0x00 5004 pa_cr2 port a control register 2 0x00 0x00 5005 port b pb_odr port b data output latch register 0x00 0x00 5006 pb_idr port b input pin value register 0xxx (1) 0x00 5007 pb_ddr port b data direction register 0x00 0x00 5008 pb_cr1 port b control register 1 0x00 0x00 5009 pb_cr2 port b control register 2 0x00 0x00 500a port c pc_odr port c data output latch register 0x00 0x00 500b pb_idr port c input pin value register 0xxx (1) 0x00 500c pc_ddr port c data direction register 0x00 0x00 500d pc_cr1 port c control register 1 0x00 0x00 500e pc_cr2 port c control register 2 0x00 0x00 500f port d pd_odr port d data output latch register 0x00 0x00 5010 pd_idr port d input pin value register 0xxx (1) 0x00 5011 pd_ddr port d data direction register 0x00 0x00 5012 pd_cr1 port d control register 1 0x02 0x00 5013 pd_cr2 port d control register 2 0x00 0x00 5014 port e pe_odr port e data output latch register 0x00 0x00 5015 pe_idr port e input pin value register 0xxx (1) 0x00 5016 pe_ddr port e data direction register 0x00 0x00 5017 pe_cr1 port e control register 1 0x00 0x00 5018 pe_cr2 port e control register 2 0x00 0x00 5019 port f pf_odr port f data output latch register 0x00 0x00 501a pf_idr port f input pin value register 0xxx (1) 0x00 501b pf_ddr port f data direction register 0x00 0x00 501c pf_cr1 port f control register 1 0x00 0x00 501d pf_cr2 port f control register 2 0x00
stm8af61xx, stm8af62xx memory and register map doc id 14952 rev 6 31/89 0x00 501e port g pg_odr port g data output latch register 0x00 0x00 501f pg_idr port g input pin value register 0xxx (1) 0x00 5020 pg_ddr port g data direction register 0x00 0x00 5021 pg_cr1 port g control register 1 0x00 0x00 5022 pg_cr2 port g control register 2 0x00 1. depends on the external circuitry. table 13. general hardware register map address block register label register name reset status 0x00 505a flash flash_cr1 flash control register 1 0x00 0x00 505b flash_cr2 flash control register 2 0x00 0x00 505c flash_ncr2 flash complementary control register 2 0xff 0x00 505d flash_fpr flash protection register 0x00 0x00 505e flash_nfpr flash complementary protection register 0xff 0x00 505f flash_iapsr flash in-application programming status register 0x40 0x00 5060 to 0x00 5061 reserved area (2 bytes) 0x00 5062 flash flash_pukr flash program memory unprotection register 0x00 0x00 5063 reserved area (1 byte) 0x00 5064 flash flash_dukr data eepr om unprotectio n register 0x00 0x00 5065 to 0x00 509f reserved area (59 bytes) 0x00 50a0 itc exti_cr1 external interrupt control register 1 0x00 0x00 50a1 exti_cr2 external interrupt control register 2 0x00 0x00 50a2 to 0x00 50b2 reserved area (17 bytes) 0x00 50b3 rst rst_sr reset status register 0xxx (1) 0x00 50b4 to 0x00 50bf reserved area (12 bytes) 0x00 50c0 clk clk_ickr internal clock control register 0x01 0x00 50c1 clk_eckr external clock control register 0x00 0x00 50c2 reserved area (1 byte) table 12. i/o port hardware register map (continued) address block register label register name reset status
memory and register map stm8af61xx, stm8af62xx 32/89 doc id 14952 rev 6 0x00 50c3 clk clk_cmsr clock master status register 0xe1 0x00 50c4 clk_swr clock master switch register 0xe1 0x00 50c5 clk_swcr clock switch control register 0xxx 0x00 50c6 clk_ckdivr clock divider register 0x18 0x00 50c7 clk_pckenr1 peripheral clock gating register 1 0xff 0x00 50c8 clk_cssr clock secu rity system register 0x00 0x00 50c9 clk_ccor configurable clock control register 0x00 0x00 50ca clk_pckenr2 periphera l clock gating register 2 0xff 0x00 50cb reserved area (1 byte) 0x00 50cc clk clk_hsitrimr hsi clock calibration trimming register 0x00 0x00 50cd clk_swimccr swim clock control register 0bxxxx xxx0 0x00 50ce to 0x00 50d0 reserved area (3 bytes) 0x00 50d1 wwdg wwdg_cr wwdg contro l register 0x7f 0x00 50d2 wwdg_wr wwdr window register 0x7f 0x00 50d3 to 0x00 50df reserved area (13 bytes) 0x00 50e0 iwdg iwdg_kr iwdg key register 0xxx (2) 0x00 50e1 iwdg_pr iwdg prescaler register 0x00 0x00 50e2 iwdg_rlr iwdg reload register 0xff 0x00 50e3 to 0x00 50ef reserved area (13 bytes) 0x00 50f0 awu awu_csr1 awu control/st atus register 1 0x00 0x00 50f1 awu_apr awu asynchronous prescaler buffer register 0x3f 0x00 50f2 awu_tbr awu timebase selection register 0x00 0x00 50f3 beep beep_csr beep contro l/status register 0x1f 0x00 50f4 to 0x00 50ff reserved area (12 bytes) table 13. general hardware register map (continued) address block register label register name reset status
stm8af61xx, stm8af62xx memory and register map doc id 14952 rev 6 33/89 0x00 5200 spi spi_cr1 spi control register 1 0x00 0x00 5201 spi_cr2 spi control register 2 0x00 0x00 5202 spi_icr spi interrupt control register 0x00 0x00 5203 spi_sr spi status register 0x02 0x00 5204 spi_dr spi data register 0x00 0x00 5205 spi_crcpr spi crc polynomial register 0x07 0x00 5206 spi_rxcrcr spi rx crc register 0xff 0x00 5207 spi_txcrcr spi tx crc register 0xff 0x00 5208 to 0x00 520f reserved area (8 bytes) 0x00 5210 i2c i2c_cr1 i2c control register 1 0x00 0x00 5211 i2c_cr2 i2c control register 2 0x00 0x00 5212 i2c_freqr i2c frequency register 0x00 0x00 5213 i2c_oarl i2c own address register low 0x00 0x00 5214 i2c_oarh i2c own address register high 0x00 0x00 5215 reserved area (1 byte) 0x00 5216 i2c_dr i2c data register 0x00 0x00 5217 i2c_sr1 i2c status register 1 0x00 0x00 5218 i2c_sr2 i2c status register 2 0x00 0x00 5219 i2c_sr3 i2c status register 3 0x00 0x00 521a i2c_itr i2c interrupt control register 0x00 0x00 521b i2c_ccrl i2c clock control register low 0x00 0x00 521c i2c_ccrh i2c clock control register high 0x00 0x00 521d i2c_triser i2c trise register 0x02 0x00 521e to 0x00 523f reserved area (24 bytes) table 13. general hardware register map (continued) address block register label register name reset status
memory and register map stm8af61xx, stm8af62xx 34/89 doc id 14952 rev 6 0x00 5240 linuart uart2_sr linuart status register 0xc0 0x00 5241 uart2_dr linuart data register 0xxx 0x00 5242 uart2_brr1 linuart baud rate register 1 0x00 0x00 5243 uart2_brr2 linuart baud rate register 2 0x00 0x00 5244 uart2_cr1 linuart control register 1 0x00 0x00 5245 uart2_cr2 linuart control register 2 0x00 0x00 5246 uart2_cr3 linuart control register 3 0x00 0x00 5247 uart2_cr4 linuart control register 4 0x00 0x00 5248 reserved 0x00 5249 uart2_cr6 linuart control register 6 0x00 0x00 524a to 0x00 524f reserved area (6 bytes) 0x00 5250 tim1 tim1_cr1 tim1 control register 1 0x00 0x00 5251 tim1_cr2 tim1 control register 2 0x00 0x00 5252 tim1_smcr tim1 slave mode control register 0x00 0x00 5253 tim1_etr tim1 external trigger register 0x00 0x00 5254 tim1_ier tim1 interrupt enable register 0x00 0x00 5255 tim1_sr1 tim1 st atus register 1 0x00 0x00 5256 tim1_sr2 tim1 st atus register 2 0x00 0x00 5257 tim1_egr tim1 event generation register 0x00 0x00 5258 tim1_ccmr1 tim1 capture/compare mode register 1 0x00 0x00 5259 tim1_ccmr2 tim1 capture/compare mode register 2 0x00 0x00 525a tim1_ccmr3 tim1 capture/compare mode register 3 0x00 0x00 525b tim1_ccmr4 tim1 capture/compare mode register 4 0x00 0x00 525c tim1_ccer1 tim1 capture/compare enable register 1 0x00 0x00 525d tim1_ccer2 tim1 capture/compare enable register 2 0x00 0x00 525e tim1_cntrh tim1 counter high 0x00 0x00 525f tim1_cntrl tim1 counter low 0x00 0x00 5260 tim1_pscrh tim1 prescaler register high 0x00 0x00 5261 tim1_pscrl tim1 prescaler register low 0x00 0x00 5262 tim1_arrh tim1 auto-reload register high 0xff 0x00 5263 tim1_arrl tim1 auto -reload register low 0xff 0x00 5264 tim1_rcr tim1 repetit ion counter register 0x00 table 13. general hardware register map (continued) address block register label register name reset status
stm8af61xx, stm8af62xx memory and register map doc id 14952 rev 6 35/89 0x00 5265 tim1 tim1_ccr1h tim1 capture/com pare register 1 high 0x00 0x00 5266 tim1_ccr1l tim1 capture/ compare register 1 low 0x00 0x00 5267 tim1_ccr2h tim1 capture/ compare register 2 high 0x00 0x00 5268 tim1_ccr2l tim1 capture/ compare register 2 low 0x00 0x00 5269 tim1_ccr3h tim1 capture/ compare register 3 high 0x00 0x00 526a tim1_ccr3l tim1 capture/ compare register 3 low 0x00 0x00 526b tim1_ccr4h tim1 capture/ compare register 4 high 0x00 0x00 526c tim1_ccr4l tim1 captur e/compare register 4 low 0x00 0x00 526d tim1_bkr tim1 break register 0x00 0x00 526e tim1_dtr tim1 d ead-time register 0x00 0x00 526f tim1_oisr tim1 output idle state register 0x00 0x00 5270 to 0x00 52ff reserved area (147 bytes) 0x00 5300 tim2 tim2_cr1 tim2 control register 1 0x00 0x00 5301 tim2_ier tim2 inte rrupt enable register 0x00 0x00 5302 tim2_sr1 tim2 status register 1 0x00 0x00 5303 tim2_sr2 tim2 status register 2 0x00 0x00 5304 tim2_egr tim2 event generation register 0x00 0x00 5305 tim2_ccmr1 tim2 capture/ compare mode register 1 0x00 0x00 5306 tim2_ccmr2 tim2 capture/ compare mode register 2 0x00 0x00 5307 tim2_ccmr3 tim2 capture/ compare mode register 3 0x00 0x00 5308 tim2_ccer1 tim2 capture/compare enable register 1 0x00 0x00 5309 tim2_ccer2 tim2 capture/compare enable register 2 0x00 0x00 530a tim2_cntrh tim2 counter high 0x00 0x00 530b tim2_cntrl tim2 counter low 0x00 00 530c0x tim2_pscr tim2 prescaler register 0x00 0x00 530d tim2_arrh tim2 auto-reload register high 0xff 0x00 530e tim2_arrl tim2 auto -reload register low 0xff 0x00 530f tim2_ccr1h tim2 captur e/compare register 1 high 0x00 0x00 5310 tim2_ccr1l tim2 capture/ compare register 1 low 0x00 0x00 5311 tim2_ccr2h tim2 captur e/compare reg. 2 high 0x00 0x00 5312 tim2_ccr2l tim2 capture/ compare register 2 low 0x00 0x00 5313 tim2_ccr3h tim2 capture/ compare register 3 high 0x00 table 13. general hardware register map (continued) address block register label register name reset status
memory and register map stm8af61xx, stm8af62xx 36/89 doc id 14952 rev 6 0x00 5314 tim2 tim2_ccr3l tim2 captur e/compare register 3 low 0x00 0x00 5315 to 0x00 531f reserved area (11 bytes) 0x00 5320 tim3 tim3_cr1 tim3 control register 1 0x00 0x00 5321 tim3_ier tim3 inte rrupt enable register 0x00 0x00 5322 tim3_sr1 tim3 st atus register 1 0x00 0x00 5323 tim3_sr2 tim3 st atus register 2 0x00 0x00 5324 tim3_egr tim3 event generation register 0x00 0x00 5325 tim3_ccmr1 tim3 capture/compare mode register 1 0x00 0x00 5326 tim3_ccmr2 tim3 capture/compare mode register 2 0x00 0x00 5327 tim3_ccer1 tim3 capture/compare enable register 1 0x00 0x00 5328 tim3_cntrh tim3 counter high 0x00 0x00 5329 tim3_cntrl tim3 counter low 0x00 0x00 532a tim3_pscr tim3 prescaler register 0x00 0x00 532b tim3_arrh tim3 auto-reload register high 0xff 0x00 532c tim3_arrl tim3 au to-reload register low 0xff 0x00 532d tim3_ccr1h tim3 captur e/compare register 1 high 0x00 0x00 532e tim3_ccr1l tim3 capture/ compare register 1 low 0x00 0x00 532f tim3_ccr2h tim3 captur e/compare register 2 high 0x00 0x00 5330 tim3_ccr2l tim3 capture/ compare register 2 low 0x00 0x00 5331 to 0x00 533f reserved area (15 bytes) 0x00 5340 tim4 tim4_cr1 tim4 control register 1 0x00 0x00 5341 tim4_ier tim4 inte rrupt enable register 0x00 0x00 5342 tim4_sr tim4 st atus register 0x00 0x00 5343 tim4_egr tim4 event generation register 0x00 0x00 5344 tim4_cntr tim4 counter 0x00 0x00 5345 tim4_pscr tim4 prescaler register 0x00 0x00 5346 tim4_arr tim4 aut o-reload register 0xff 0x00 5347 to 0x00 53df reserved area (185 bytes) table 13. general hardware register map (continued) address block register label register name reset status
stm8af61xx, stm8af62xx memory and register map doc id 14952 rev 6 37/89 0x00 53e0 adc adc _db0rh adc data buffer register 0 high 0x00 0x00 53e1 adc _db0rl adc data buffer register 0 low 0x00 0x00 53e2 adc _db1rh adc data buffer register 1 high 0x00 0x00 53e3 adc _db1rl adc data buffer register 1 low 0x00 0x00 53e4 adc _db2rh adc data buffer register 2 high 0x00 0x00 53e5 adc _db2rl adc data buffer register 2 low 0x00 0x00 53e6 adc _db3rh adc data buffer register 3 high 0x00 0x00 53e7 adc _db3rl adc data buffer register 3 low 0x00 0x00 53e8 adc _db4rh adc data buffer register 4 high 0x00 0x00 53e9 adc _db4rl adc data buffer register 4 low 0x00 0x00 53ea adc _db5rh adc data buffer register 5 high 0x00 0x00 53eb adc _db5rl adc data buffer register 5 low 0x00 0x00 53ec adc _db6rh adc data buffer register 6 high 0x00 0x00 53ed adc _db6rl adc data buffer register 6 low 0x00 0x00 53ee adc _db7rh adc data buffer register 7 high 0x00 0x00 53ef adc _db7rl adc data buffer register 7 low 0x00 0x00 53f0 adc _db8rh adc data buffer register 8 high 0x00 0x00 53f1 adc _db8rl adc data buffer register 8 low 0x00 0x00 53f2 adc _db9rh adc data buffer register 9 high 0x00 0x00 53f3 adc _db9rl adc data buffer register 9 low 0x00 0x00 53f4 to 0x00 53ff reserved area (12 bytes) 0x00 5400 adc adc _csr adc control/st atus register 0x00 0x00 5401 adc_cr1 adc configuration register 1 0x00 0x00 5402 adc_cr2 adc configuration register 2 0x00 0x00 5403 adc_cr3 adc configuration register 3 0x00 0x00 5404 adc_drh adc data register high 0xxx 0x00 5405 adc_drl adc data register low 0xxx 0x00 5406 adc_tdrh adc schmitt trigger disable register high 0x00 0x00 5407 adc_tdrl adc schmitt trigger disable register low 0x00 0x00 5408 adc _htrh adc high threshold register high 0xff 0x00 5409 adc_htrl adc high threshold register low 0x03 0x00 540a adc _ltrh adc low threshold register high 0x00 table 13. general hardware register map (continued) address block register label register name reset status
memory and register map stm8af61xx, stm8af62xx 38/89 doc id 14952 rev 6 0x00 540b adc adc_ltrl adc low threshold register low 0x00 0x00 540c adc _awsrh adc watchdog status register high 0x00 0x00 540d adc_awsrl adc watchdog status register low 0x00 0x00 540e adc _awcrh adc watchdog control register high 0x00 0x00 540f adc _awcrh adc watchdog control register low 0x00 0x00 5410 to 0x00 541f reserved area (16 bytes) 1. depends on the previous reset source. 2. write only register. table 13. general hardware register map (continued) address block register label register name reset status table 14. cpu/swim/debug module/interrupt controller registers address block register label register name reset status 0x00 7f00 cpu (1) a accumulator 0x00 0x00 7f01 pce program counter extended 0x00 0x00 7f02 pch program counter high 0x80 0x00 7f03 pcl program counter low 0x00 0x00 7f04 xh x index register high 0x00 0x00 7f05 xl x index register low 0x00 0x00 7f06 yh y index register high 0x00 0x00 7f07 yl y index register low 0x00 0x00 7f08 sph stack pointer high 0x17 (2) 0x00 7f09 spl stack pointer low 0xff 0x00 7f0a cc condition code register 0x28 0x00 7f0b to 0x00 7f5f reserved area (85 bytes) 0x00 7f60 cpu cfg_gcr global c onfiguration register 0x00 0x00 7f70 itc itc_spr1 interrupt software priority register 1 0xff 0x00 7f71 itc_spr2 interrupt software priority register 2 0xff 0x00 7f72 itc_spr3 interrupt software priority register 3 0xff 0x00 7f73 itc_spr4 interrupt software priority register 4 0xff 0x00 7f74 itc_spr5 interrupt software priority register 5 0xff 0x00 7f75 itc_spr6 interrupt software priority register 6 0xff 0x00 7f76 to 0x00 7f79 reserved area (4 bytes) 0x00 7f80 swim swim_csr swim control status register 0x00
stm8af61xx, stm8af62xx memory and register map doc id 14952 rev 6 39/89 0x00 7f81 to 0x00 7f8f reserved area (15 bytes) 0x00 7f90 dm dm_bk1re dm breakpoint 1 register extended byte 0xff 0x00 7f91 dm_bk1rh dm breakpoint 1 register high byte 0xff 0x00 7f92 dm_bk1rl dm breakpoint 1 register low byte 0xff 0x00 7f93 dm_bk2re dm breakpoint 2 register extended byte 0xff 0x00 7f94 dm_bk2rh dm breakpoint 2 register high byte 0xff 0x00 7f95 dm_bk2rl dm breakpoint 2 register low byte 0xff 0x00 7f96 dm_cr1 dm debug module control register 1 0x00 0x00 7f97 dm_cr2 dm debug module control register 2 0x00 0x00 7f98 dm_csr1 dm debug module control/status register 1 0x10 0x00 7f99 dm_csr2 dm debug module control/status register 2 0x00 0x00 7f9a dm_enfctr dm enab le function register 0xff 0x00 7f9b to 0x00 7f9f reserved area (5 bytes) 1. accessible by debug module only 2. product dependent value, see figure 5: register and memory map of stm8a products . table 14. cpu/swim/debug module/interrupt controller registers (continued) address block register label register name reset status table 15. temporary memory unprotection registers address block register label register name reset status 0x00 5800 tmu tmu_k1 temporary memory unprotection key register 1 0x00 0x00 5801 tmu_k2 temporary memory unprotection key register 2 0x00 0x00 5802 tmu_k3 temporary memory unprotection key register 3 0x00 0x00 5803 tmu_k4 temporary memory unprotection key register 4 0x00 0x00 5804 tmu_k5 temporary memory unprotection key register 5 0x00 0x00 5805 tmu_k6 temporary memory unprotection key register 6 0x00 0x00 5806 tmu_k7 temporary memory unprotection key register 7 0x00 0x00 5807 tmu_k8 temporary memory unprotection key register 8 0x00 0x00 5808 tmu_csr temporary memory unprotection control and status register 0x00
interrupt table stm8af61xx, stm8af62xx 40/89 doc id 14952 rev 6 8 interrupt table table 16. stm8a interrupt table priority source block description interrupt vector address wakeup from halt comments ? reset reset 0x00 6000 yes reset vector in rom ? trap sw interrupt 0x00 8004 ? ? 0 tli external top level interrupt 0x00 8008 ? ? 1 awu auto-wakeup from halt 0x00 800c yes ? 2 clock controller main clock controller 0x00 8010 ? ? 3 misc ext interrupt e0 0x00 8014 yes port a interrupts 4 misc ext interrupt e1 0x00 8018 yes port b interrupts 5 misc ext interrupt e2 0x00 801c yes port c interrupts 6 misc ext interrupt e3 0x00 8020 yes port d interrupts 7 misc ext interrupt e4 0x00 8024 yes port e interrupts 8 reserved (1) 1. all reserved and unused interrupts must be init ialized with ?iret? for robust programming. ???? 9 reserved (1) ???? 10 spi end of transfer 0x00 8030 yes ? 11 timer 1 update/overflow/ trigger/break 0x00 8034 ? ? 12 timer 1 capture/compare 0x00 8038 ? ? 13 timer 2 update/overflow 0x00 803c ? ? 14 timer 2 capture/compare 0x00 8040 ? ? 15 timer 3 update/overflow 0x00 8044 ? ? 16 timer 3 capture/compare 0x00 8048 ? ? 17 reserved (1) ???? 18 reserved (1) ???? 19 i 2 c i 2 c interrupts 0x00 8054 yes ? 20 linuart tx complete/error 0x00 8058 ? ? 21 linuart receive data full reg. 0x00 805c ? ? 22 adc end of conversion 0x00 8060 ? ? 23 timer 4 update/overflow 0x00 8064 ? ? 24 eeprom end of programming/ write in not allowed area 0x00 8068 ? ?
stm8af61xx, stm8af62xx option bytes doc id 14952 rev 6 41/89 9 option bytes option bytes contain configurations for device hardware features as well as the memory protection of the device. they are stored in a dedicated block of the memory. each option byte has to be stored twice, for redundancy, in a regular form (optx) and a complemented one (noptx), except for the rop (read-out protection) option byte and option bytes 8 to 16. option bytes can be modified in icp mode (v ia swim) by accessing the eeprom address shown in ta b l e 17: option bytes below. option bytes can also be modified ?on the fly? by the application in iap mode, except the rop and ubc options that can only be toggled in icp mode (via swim). refer to the stm8 flash programming manual (pm0051) and stm8 swim communication protocol and debug module user manual (um0470) for information on swim programming procedures. table 17. option bytes addr. option name option byte no. option bits factory default setting 765 4 3 2 1 0 0x00 4800 read-out protection (rop) opt0 rop[7:0] 0x00 0x00 4801 user boot code (ubc) opt1 reserved ubc[5:0] 0x00 0x00 4802 nopt1 reserved nubc[5:0] 0xff 0x00 4803 alternate function remapping (afr) opt2 afr7 afr6 afr5 afr4 afr3 afr2 afr1 afr0 0x00 0x00 4804 nopt2 nafr 7 nafr 6 nafr 5 nafr 4 nafr 3 nafr 2 nafr 1 nafr 0 0xff 0x00 4805 watchdog option opt3 reserved 16mhz trim0 lsi _en iwdg _hw wwdg _hw wwdg _halt 0x00 0x00 4806 nopt3 reserved n16mhz trim0 nlsi _en niwdg _hw nwwd g_hw nwwg _halt 0xff 0x00 4807 clock option opt4 reserved ext clk ckawu sel prs c1 prs c0 0x00 0x00 4808 nopt4 reserved next clk nckaw usel npr sc1 npr sc0 0xff 0x00 4809 hse clock startup opt5 hsecnt[7:0] 0x00 0x00 480a nopt5 nhsecnt[7:0] 0xff
option bytes stm8af61xx, stm8af62xx 42/89 doc id 14952 rev 6 0x00 480b tmu opt6 tmu[3:0] 0x00 0x00 480c nopt6 ntmu[3:0] 0xff 0x00 480d flash wait states opt7 reserved wait state 0x00 0x00 480e nopt7 reserved nwait state 0xff 0x00 480f reserved 0x00 4810 tmu opt8 tmu_key 1 [7:0] 0x00 0x00 4811 opt9 tmu_key 2 [7:0] 0x00 0x00 4812 opt10 tmu_key 3 [7:0] 0x00 0x00 4813 opt11 tmu_key 4 [7:0] 0x00 0x00 4814 opt12 tmu_key 5 [7:0] 0x00 0x00 4815 opt13 tmu_key 6 [7:0] 0x00 0x00 4816 opt14 tmu_key 7 [7:0] 0x00 0x00 4817 opt15 tmu_key 8 [7:0] 0x00 0x00 4818 opt16 tmu_maxatt [7:0] 0xc7 0x00 4819 to 487d reserved 0x00 487e boot- loader (1) opt17 bl [7:0] 0x00 0x00 487f nopt17 nbl[7:0] 0xff 1. this option consists of two bytes that must have a complement ary value in order to be valid. if the option is invalid, it has no effect on emc reset. table 17. option bytes (continued) addr. option name option byte no. option bits factory default setting 765 4 3 2 1 0
stm8af61xx, stm8af62xx option bytes doc id 14952 rev 6 43/89 table 18. option byte description option byte no. description opt0 rop[7:0]: memory readout protection (rop) 0xaa: enable readout protection (write access via swim protocol) note: refer to the stm8s and stm8a microcontroller families reference manual (rm0016) section on flash/eeprom memory readout protection for details. opt1 ubc[5:0]: user boot code area 0x00: no ubc, no write-protection 0x01: page 0 to 1 defined as ubc, memory write-protected 0x02: page 0 to 3 defined as ubc, memory write-protected 0x03 to 0x3f: pages 4 to 63 defined as ubc, memory write-protected note: refer to the stm8s and stm8a microcontroller families reference manual (rm0016) sectio n on flash/eeprom write protection for more details. opt2 afr7: alternate function remapping option 7 0: port d4 alternate function = tim2_ch1 1: port d4 alternate function = beep afr6: alternate function remapping option 6 0: port b5 alternate function = ai n5, port b4 alternate function = ain4 1: port b5 alternate function = i 2 c_sda, port b4 alternate function = i 2 c_scl. afr5: alternate function remapping option 5 0: port b3 alternate function = ai n3, port b2 alternate function = ain2, port b1 alternate function = ain1, port b0 alternate function = ain0. 1: port b3 alternate function = ti m1_etr, port b2 alternate function = tim1_ch3n, port b1 alternate functi on = tim1_ch2n, port b0 alternate function = tim1_ch1n. afr4: alternate function remapping option 4 reserved, bit must be kept at "0" afr3: alternate function remapping option 3 0: port d0 alternate function = tim3_ch2 1: port d0 alternate function = tim1_bkin afr2: alternate function remapping option 2 0: port d0 alternate function = tim3_ch2 1: port d0 alternate function = clk_cco note: afr2 option has priority over afr3 if both are activated afr1: alternate function remapping option 1 0: port a3 alternate function = ti m2_ch3, port d2 alternate function tim3_ch1. 1: port a3 alternate function = ti m3_ch1, port d2 alternate function tim2_ch3. afr0: alternate function remapping option 0 0: port d3 alternate function = tim2_ch2 1: port d3 alternate function = adc_etr
option bytes stm8af61xx, stm8af62xx 44/89 doc id 14952 rev 6 opt3 hsitrim: trimming option for 16 mhz internal rc oscillator 0: 3-bit on-the-fly trimming (compatible with devices based on the 128k silicon) 1: 4-bit on-the-fly trimming lsi_en: low speed internal clock enable 0: lsi clock is not available as cpu clock source 1: lsi clock is available as cpu clock source iwdg_hw: independent watchdog 0: iwdg independent watchdog activated by software 1: iwdg independent watchdog activated by hardware wwdg_hw: window watchdog activation 0: wwdg window watchdog activated by software 1: wwdg window watchdog activated by hardware wwdg_halt: window watchdog reset on halt 0: no reset generated on halt if wwdg active 1: reset generated on halt if wwdg active opt4 extclk: external clock selection 0: external crystal c onnected to oscin/oscout 1: external clock signal on oscin ckawusel: auto-wakeup unit/clock 0: lsi clock source selected for awu 1: hse clock with prescaler selected as clock source for awu prsc[1:0]: awu clock prescaler 00: reserved 01: 16 mhz to 128 khz prescaler 10: 8 mhz to 128 khz prescaler 11: 4 mhz to 128 khz prescaler opt5 hsecnt[7:0]: hse crystal oscillator stabilization time this configures the stabilization ti me to 0.5, 8, 128, and 2048 hse cycles with corresponding option byte values of 0xe1, 0xd2, 0xb4, and 0x00. opt6 tmu [3:0]: enable temporary memory unprotection 0101: tmu disabled (permanent rop). any other value: tmu enabled. opt7 reserved opt8 tmu_key 1 [7:0]: temporary unprotection key 0 temporary unprotection key: must be different from 0x00 or 0xff opt9 tmu_key 2 [7:0]: temporary unprotection key 1 temporary unprotection key: must be different from 0x00 or 0xff opt10 tmu_key 3 [7:0]: temporary unprotection key 2 temporary unprotection key: must be different from 0x00 or 0xff opt11 tmu_key 4 [7:0]: temporary unprotection key 3 temporary unprotection key: must be different from 0x00 or 0xff table 18. option byte description (continued) option byte no. description
stm8af61xx, stm8af62xx option bytes doc id 14952 rev 6 45/89 opt12 tmu_key 5 [7:0]: temporary unprotection key 4 temporary unprotection key: must be different from 0x00 or 0xff opt13 tmu_key 6 [7:0]: temporary unprotection key 5 temporary unprotection key: must be different from 0x00 or 0xff opt14 tmu_key 7 [7:0]: temporary unprotection key 6 temporary unprotection key: must be different from 0x00 or 0xff opt15 tmu_key 8 [7:0]: temporary unprotection key 7 temporary unprotection key: must be different from 0x00 or 0xff opt16 tmu_maxatt [7:0]: tmu access failure counter tmu_maxatt can be initialized with the desired value only if tmu is disabled (tmu[3:0]=0101 in opt6 option byte). when tmu is enabled, any attempt to temporary remove the readout protection by using wrong key va lues increments the counter. when the option byte value reaches 0x08, the flash memory and data eeprom are erased. opt17 bl [7:0]: bootloader enable if this option byte is set to 0x55 (complementary value 0xaa) the bootloader program is activated also in case of a programmed code memory (for more details, see the bootloader user manual, um0560). table 18. option byte description (continued) option byte no. description
electrical characteristics stm8af61xx, stm8af62xx 46/89 doc id 14952 rev 6 10 electrical characteristics 10.1 parameter conditions unless otherwise specified, all voltages are referred to v ss . 10.1.1 minimum and maximum values unless otherwise specified the minimum and ma ximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100 % of the devices with an ambient temperature at t a = -40 c, t a = 25 c, and t a = t amax (given by the selected temperature range). data based on characterization results, desi gn simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. 10.1.2 typical values unless otherwise specified, typical data are based on t a = 25 c, v dd = 5.0 v. they are given only as design guidelines and are not tested. typical adc accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range . 10.1.3 typical curves unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 10.1.4 loading capacitor the loading conditions used for pin parameter measurement are shown in figure 6 . figure 6. pin loading conditions 50 pf stm8a pin
stm8af61xx, stm8af62xx electrical characteristics doc id 14952 rev 6 47/89 10.1.5 pin input voltage the input voltage measurement on a pin of the device is described in figure 7 . figure 7. pin input voltage 10.2 absolute maximum ratings stresses above those listed as ?absolute ma ximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device under these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. v in stm8a pin table 19. voltage characteristics symbol ratings min max unit v ddx - v ss supply voltage (including v dda and v ddio ) (1) 1. all power (v dd , v ddio , v dda ) and ground (v ss , v ssio , v ssa ) pins must always be connected to the external power supply -0.3 6.5 v v in input voltage on true open drain pins (pe1, pe2) (2) 2. i inj(pin) must never be exceeded. this is implicitly insured if v in maximum is respected. if v in maximum cannot be respected, the injection current must be limited externally to the i inj(pin) value. a positive injection is induced by v in > v dd while a negative injection is induced by v in < v ss . for true open-drain pads, there is no positive injection current, and the corresponding v in maximum must always be respected v ss - 0.3 6.5 v input voltage on any other pin (2) v ss - 0.3 v dd + 0.3 |v ddx - v dd | variations between different power pins - 50 mv |v ssx - v ss | variations between all the different ground pins - 50 v esd electrostatic discharge voltage see absolute maximum ratings (electrical sensitivity) on page 72
electrical characteristics stm8af61xx, stm8af62xx 48/89 doc id 14952 rev 6 table 20. current characteristics symbol ratings max. unit i vddio total current into v ddio power lines (source) (1)(2)(3) 1. all power (v dd , v ddio , v dda ) and ground (v ss , v ssio , v ssa ) pins must always be connected to the external supply. 2. the total limit applies to the sum of operation and injected currents. 3. v ddio includes the sum of the positive injection currents. v ssio includes the sum of the negative injection currents. 100 ma i vssio total current out of v ss io ground lines (sink) (1)(2)(3) 100 i io output current sunk by any i/o and control pin 20 output current source by any i/os and control pin -20 i inj(pin) (4) 4. this condition is implicitly insured if v in maximum is respected. if v in maximum cannot be respected, the injection current must be limited externally to the i inj(pin) value. a positive inje ction is induced by v in > v dd while a negative injecti on is induced by v in < v ss . for true open-drain pads, ther e is no positive injection current allowed and the corresponding v in maximum must always be respected. injected current on any pin 10 i inj(tot) sum of injected currents 50 table 21. thermal characteristics symbol ratings value unit t stg storage temperature range ? 65 to 150 c t j maximum junction temperature 160 table 22. operating lifetime (1) 1. for detailed mission profile analysis, plea se contact your local st sales office. symbol ratings value unit olf conforming to aec-q100 rev g ? 40 to 125 c grade 1 ? 40 to 150 c grade 0
stm8af61xx, stm8af62xx electrical characteristics doc id 14952 rev 6 49/89 10.3 operating conditions table 23. general operating conditions symbol parameter conditions min max unit f cpu internal cpu clock frequency t a = -40 c to 150 c 0 16 mhz v dd/ v ddio standard operating voltage - 3.0 5.5 v v cap (1) 1. care should be taken when selecting the capacitor, due to its tolerance, as well as the parameter dependency on temperature, dc bias and frequency in addi tion to other factors. the parameter maximum value must be respected for the full application range. c ext : capacitance of external capacitor 470 3300 nf esr of external capacitor at 1 mhz (2) 2. this frequency of 1 mhz as a condition for v cap parameters is given by des ign of internal regulator. -0.3 esl of external capacitor - 15 nh p d power dissipation (all temperature ranges) lqfp32 - 85 mw vfqfpn32 - 200 lqfp48 - 88 t a ambient temperature suffix a -40 85 c suffix b 105 suffix c 125 suffix d (3) 3. available on stm8af62xx devices only. 150 t j junction temperature range suffix a 90 suffix b 110 suffix c 130 suffix d (3) 155
electrical characteristics stm8af61xx, stm8af62xx 50/89 doc id 14952 rev 6 figure 8. f cpumax versus v dd 1. this figure is valid only for stm8af62xx devices. table 24. operating conditions at power-up/power-down symbol parameter conditions min typ max unit t vdd v dd rise time rate - 2 (1) 1. guaranteed by design, not tested in production - s/v v dd fall time rate - 2 (1) - t temp reset release delay v dd rising - 3 - ms reset generation delay v dd falling - 3 - s v it+ power-on reset threshold (2) 2. if v dd is below 3 v, the code execution is guaranteed above the v it- and v it+ thresholds. ram content is kept. the eeprom programming sequence must not be initiated. - 2.65 2.8 2.95 v v it- brown-out reset threshold - 2.58 2.73 2.88 v hys(bor) brown-out reset hysteresis -- 70 (1) -mv f cpu [mhz] supply voltage [v] 24 12 8 4 0 3.0 4.0 5.0 functionality functionality guaranteed @ t a -40 to 150 c not guaranteed in this area 16 5.5
stm8af61xx, stm8af62xx electrical characteristics doc id 14952 rev 6 51/89 10.3.1 vcap external capacitor stabilization for the ma in regulator is achieved conne cting an external capacitor c ext to the v cap pin. c ext is specified in ta b l e 23 . care should be taken to limit the series inductance to less than 15 nh. figure 9. external capacitor c ext 1. legend: esr is the equivalent series resi stance and esl is the equivalent inductance. 10.3.2 supply current characteristics the current consumption is measured as described in figure 6 on page 46 and figure 7 on page 47 . if not explicitly stated, general conditions of temperature and voltage apply. c rleak esr esl table 25. total current consumption in run, wait and slow mode. general conditions for v dd apply, t a = ? 40 to 150 c symbol parameter con ditions typ max unit i dd(run) (1) 1. the current due to i/o utilization is not taken into account in these values. supply current in run mode all peripherals clocked, code executed from flash program memory, hse external clock (without resonator) f cpu = 16 mhz 7.4 14 ma f cpu = 8 mhz 4.0 7.4 (2) 2. values not tested in production. design guidelines only. f cpu = 4 mhz 2.4 4.1 (2) f cpu = 2 mhz 1.5 2.5 i dd(run) (1) supply current in run mode all peripherals clocked, code executed from ram and eeprom, hse external clock (without resonator) f cpu = 16 mhz 3.7 5.0 f cpu = 8 mhz 2.2 3.0 (2) f cpu = 4 mhz 1.4 2.0 (2) f cpu = 2 mhz 1.0 1.5 i dd(wfi) (1) supply current in wait mode cpu stopped, all peripherals off, hse external clock f cpu = 16 mhz 1.65 2.5 f cpu = 8 mhz 1.15 1.9 (2) f cpu = 4 mhz 0.90 1.6 (2) f cpu = 2 mhz 0.80 1.5 i dd(slow) (1) supply current in slow mode f cpu scaled down, all peripherals off, code executed from ram ext. clock 16 mhz f cpu = 125 khz 1.50 1.95 lsi internal rc f cpu = 128 khz 1.50 1.80 (2)
electrical characteristics stm8af61xx, stm8af62xx 52/89 doc id 14952 rev 6 current consumption for on-chip peripherals table 26. total current consumption in halt and active-halt modes. general conditions for v dd apply, t a = ? 40 to 55 c symbol parameter conditions typ max unit main voltage regulator (mvr) (1) flash mode (2) clock source and specific temperature condition i dd(h) supply current in halt mode off power- down clocks stopped 5 35 (3) a clocks stopped, t a = 25 c 525 i dd(ah) supply current in active-halt mode with regulator on on power- down ext. clock 16 mhz f master = 125 khz 770 900 (3) lsi clock 128 khz 150 230 (3) supply current in active-halt mode with regulator off off power- down lsi clock 128 khz 25 42 (3) lsi clock 128 khz, t a = 25 c 25 30 t wu(ah) wakeup time from active- halt mode with regulator on on operating mode t a = -40 to 150 c 10 30 (3) s wakeup time from active- halt mode with regulator off off 50 80 (3) 1. configured by the regah bit in the clk_ickr register. 2. configured by the ahalt bit in the flash_cr1 register. 3. data based on characterization results. not tested in production. table 27. oscillator current consumption symbol parameter conditions typ max (1) 1. during startup, the oscillator cu rrent consumption may reach 6 ma. unit i dd(osc) hse oscillator current consumption (2) 2. the supply current of the oscillator can be further opt imized by selecting a high quality resonator with small r m value. refer to crystal manufacturer for more details quartz or ceramic resonator, cl = 33 pf v dd = 5 v f osc = 24 mhz 1 2.0 (3) 3. informative data. ma f osc = 16 mhz 0.6 - f osc = 8 mhz 0.57 - i dd(osc) hse oscillator current consumption (2) quartz or ceramic resonator, cl = 33 pf v dd = 3.3 v f osc = 24 mhz 0.5 1.0 (3) f osc = 16 mhz 0.25 - f osc = 8 mhz 0.18 -
stm8af61xx, stm8af62xx electrical characteristics doc id 14952 rev 6 53/89 current consumption curves figure 10 to figure 15 show typical current consumption measured with code executing in ram. table 28. programming current consumption symbol parameter conditions typ max unit i dd(prog) programming current v dd = 5 v, -40 c to 150 c, erasing and programming data or flash program memory 1.0 1.7 ma table 29. typical peripheral current consumption v dd = 5.0 v (1) 1. typical values not tested in production. since the perip herals are powered by an internally regulated, constant digital supply voltage, the values are similar in the full supply voltage range. symbol parameter typ. f master = 2 mhz typ. f master = 16 mhz unit i dd(tim1) tim1 supply current (2) 2. data based on a differential i dd measurement between no peripheral clocked and a single active peripheral. this measurement does not include the pad toggling consumption. 0.03 0.23 ma i dd(tim2) tim2 supply current (2) 0.02 0.12 i dd(tim3) tim3 supply current (2) 0.01 0.1 i dd(tim4) tim4 supply current (2) 0.004 0.03 i dd(linuart) linuart supply current (2) 0.03 0.11 i dd(spi) spi supply current (2) 0.01 0.04 i dd(i 2 c) i 2 c supply current (2) 0.02 0.06 i dd(awu) awu supply current (2) 0.003 0.02 i dd(tot_dig) all digital peripherals on 0.22 1 i dd(adc) adc supply current when converting (3) 3. data based on a differential i dd measurement between reset configuration and continuous a/d conversions. 0.93 0.95 figure 10. typ. i dd(run)hse vs. v dd @f cpu = 16 mhz, peripheral = on figure 11. typ. i dd(run)hse vs. f cpu @ v dd = 5.0 v, peripheral = on 0 1 2 3 4 5 6 7 8 9 10 2.533.544.555.56 v dd [v] i dd(run)hse [ma] 25c 85c 12 5 c 0 1 2 3 4 5 6 7 8 9 10 0 5 10 15 20 25 30 fcpu [mhz] i dd(run)hse [ma] 25c 85c 12 5 c
electrical characteristics stm8af61xx, stm8af62xx 54/89 doc id 14952 rev 6 10.3.3 external clock sources and timing characteristics hse user external clock subject to general operating conditions for v dd and t a . figure 12. typ. i dd(run)hsi vs. v dd @ f cpu = 16 mhz, peripheral = off figure 13. typ. i dd(wfi)hse vs. v dd @ f cpu = 16 mhz, peripheral = on 0 1 2 3 4 2.5 3.5 4.5 5.5 6.5 vdd [v] idd(run)hsi [ma] 25c 85c 125c 0 1 2 3 4 5 6 2.5 3.5 4.5 5.5 6.5 vdd [v] idd(wfi)hse [ma] 25c 85c 125c figure 14. typ. i dd(wfi)hse vs. f cpu @ v dd = 5.0 v, peripheral = on figure 15. typ. i dd(wfi)hsi vs. v dd @ f cpu = 16 mhz, peripheral = off 0 1 2 3 4 5 6 0 5 10 15 20 25 30 fcpu [mhz] i dd(wfi)hse [ma] 25c 85c 12 5 c 0 0. 5 1 1. 5 2 2. 5 2. 5 3 3. 5 4 4. 5 5 5. 5 6 v dd [v] i dd(wfi)hsi [ma] 25c 85c 12 5 c table 30. hse user external clock characteristics symbol parameter conditions min typ max unit f hse_ext user external clock source frequency t a is -40 to 150 c 0 (1) 1. in css is used, the external clock must have a frequency above 500 khz. -16mhz v hsedhl comparator hysteresis - 0.1 x v dd -- v v hseh oscin input pin high level voltage - 0.7 x v dd -v dd v hsel oscin input pin low level voltage -v ss - 0.3 x v dd i leak_hse oscin input leakage current v ss < v in < v dd -1 - +1 a
stm8af61xx, stm8af62xx electrical characteristics doc id 14952 rev 6 55/89 figure 16. hse external clock source hse crystal/ceramic resonator oscillator the hse clock can be supplied using a crystal/ce ramic resonator oscillator of up to 16 mhz. all the information given in this paragraph is based on characterization results with specified typical external components. in the application, the resonator and the load capacitors have to be placed as close as possible to the oscilla tor pins in order to minimize output distortion and startup stabilization time. refer to the crys tal resonator manufactur er for more details (frequency, package, accuracy...). figure 17. hse oscillator circuit diagram oscin f hse external clock stm8a source v hsel v hseh table 31. hse oscillator characteristics symbol parameter conditions min typ max unit r f feedback resistor - - 220 - k c l1 /c l2 (1) recommended load capacitance - - - 20 pf g m oscillator transconductance - 5 - - ma/v t su(hse) (2) startup time v dd is stabilized -2.8 -ms 1. the oscillator needs two load capacitors, c l1 and c l2 , to act as load for the crysta l. the total load capacitance (c load ) is (c l1 * c l2 )/(c l1 + c l2 ). if c l1 = c l2 , c load = c l1 / 2. some oscillators have built-in load capacitors, c l1 and c l2 . 2. this value is the startup time, measured from the moment it is enabled (by software) until a stabilized 16 mhz oscillation is reached. it can vary with the crystal type that is used. oscout oscin f hse to core c l1 c l2 r f stm8a resonator current control g m r m c m l m c o resonator
electrical characteristics stm8af61xx, stm8af62xx 56/89 doc id 14952 rev 6 hse oscillator critical g m formula the crystal characteristics have to be checked with the following formula: g m g mcrit ? where g mcrit can be calculated with the crystal parameters as follows: g mcrit 2 hse f () 2 r m 2co c + () 2 = r m : notional resistance (see crystal specification) l m : notional inductance (see crystal specification) c m : notional capacitance (s ee crystal specification) co: shunt capacitance (see c rystal specification) c l1 = c l2 = c: grounded external capacitance 10.3.4 internal clock sources and timing characteristics subject to general operating conditions for v dd and t a . high speed internal rc oscillator (hsi) table 32. hsi oscillator characteristics symbol parameter conditions min typ max unit f hsi frequency - 16 - mhz acc hs hsi oscillator user trimming accuracy trimmed by the application for any v dd and t a conditions -1 (1) 1. depending on option byte setting (opt3 and nopt3) -1 (1) % -0.5 (1) -0.5 (1) hsi oscillator accuracy (factory calibrated) v dd = 3.0 v v dd 5.5 v, -40 c t a 150 c -5 - 5 t su(hsi) hsi oscillator wakeup time - - 2 (2) 2. guaranteed by characterizati on, not tested in production s
stm8af61xx, stm8af62xx electrical characteristics doc id 14952 rev 6 57/89 figure 18. typical hsi frequency vs v dd low speed internal rc oscillator (lsi) subject to general operating conditions for v dd and t a . figure 19. typical lsi frequency vs v dd table 33. lsi oscillator characteristics symbol parameter conditions min typ max unit f lsi frequency - 112 128 144 khz t su(lsi) lsi oscillator wakeup time - - - 7 (1) 1. data based on characterization results, not tested in production. s -3% -2% -1% 0% 1% 2% 3% 2.5 3 3.5 4 4.5 5 5.5 6 v dd [v] hsi frequency variation [%] -40c 25c 85c 125c -3% -2% -1% 0% 1% 2% 3% 2.5 3 3.5 4 4.5 5 5.5 6 v dd [v] lsi frequency variation [%] 25c
electrical characteristics stm8af61xx, stm8af62xx 58/89 doc id 14952 rev 6 10.3.5 memory characteristics flash program memory/data eeprom memory general conditions: t a = - 40 to 150 c . table 34. flash program memory/data eeprom memory symbol parameter conditions min typ max unit v dd operating voltage (all modes, execution/write/erase) f cpu is 0 to 16 mhz with 0 ws 3.0 - 5.5 v v dd operating voltage (code execution) f cpu is 0 to 16 mhz with 0 ws 2.6 - 5.5 t prog standard programming time (including erase) for byte/word/block (1 byte/4 bytes/128 bytes) --66.6 ms fast programming time for 1 block (128 bytes) --33.3 t erase erase time for 1 block (128 bytes) - - 3 3.3 ms table 35. flash program memory symbol parameter condition min max unit t we temperature for writing and erasing - -40 150 c n we flash program memory endurance (erase/write cycles) (1) 1. the physical granularity of the memo ry is four bytes, so cycling is performed on four bytes even when a write/erase operation addresses a single byte. t a = 25 c 1000 - cycles t ret data retention time t a = 25 c 40 - years t a = 55 c 20 - table 36. data memory symbol parameter condition min max unit t we temperature for writing and erasing -40 150 c n we data memory endurance (1) (erase/write cycles) 1. the physical granularity of the memo ry is four bytes, so cycling is performed on four bytes even when a write/erase operation addresses a single byte. t a = 25 c 300 k - cycles t a = -40c to 125 c 100 k (2) 2. more information on the relationship between data re tention time and number of write/erase cycles is available in a separat e technical document. - t ret data retention time t a = 25 c 40 (2)(3) 3. retention time for 256b of data memory after up to 1000 cycles at 125 c. - years t a = 55 c 20 (2)(3) -
stm8af61xx, stm8af62xx electrical characteristics doc id 14952 rev 6 59/89 10.3.6 i/o port pin characteristics general characteristics subject to general operating conditions for v dd and t a unless otherwise specified. all unused pins must be kept at a fixed voltage, us ing the output mode of the i/o for example or an external pull-up or pull-down resistor. table 37. i/o static characteristics symbol parameter conditions min typ max unit v il input low level voltage -0.3 v 0.3 x v dd ? v ih input high level voltage 0.7 x v dd v dd + 0.3 v v hys hysteresis (1) - 0.1 x v dd - v oh output high level voltage standard i/0, v dd = 5 v, i = 3 ma v dd - 0.5 v - - standard i/0, v dd = 3 v, i = 1.5 ma v dd - 0.4 v - - v ol output low level voltage high sink and true open drain i/0, v dd = 5 v i = 8 ma --0.5 v standard i/0, v dd = 5 v i = 3 ma --0.6 standard i/0, v dd = 3 v i = 1.5 ma --0.4 r pu pull-up resistor v dd = 5 v, v in = v ss 35 50 65 k t r , t f rise and fall time (10% - 90%) fast i/os load = 50 pf --35 (2) ns standard and high sink i/os load = 50 pf - - 125 (2) fast i/os load = 20 pf 20 (2) standard and high sink i/os load = 20 pf 50 (2) i lkg digital input pad leakage current v ss v in v dd --1a i lkg ana analog input pad leakage current v ss v in v dd -40 c < t a < 125 c - - 250 na v ss v in v dd -40 c < t a < 150 c - - 500 i lkg(inj) leakage current in adjacent i/o (3) injection current 4 ma - - 1 (3) a i ddio total current on either v ddio or v ssio including injection currents - - 60 ma 1. hysteresis voltage between schmitt trigger switching levels . based on characterization results, not tested in production.
electrical characteristics stm8af61xx, stm8af62xx 60/89 doc id 14952 rev 6 figure 20. typical v il and v ih vs v dd @ four temperatures figure 21. typical pull-up resistance r pu vs v dd @ four temperatures 2. guaranteed by design. 3. data based on characterization results, not tested in production. 0 1 2 3 4 5 6 2.5 3 3.5 4 4.5 5 5.5 6 v dd [v] v il / v ih [v] -40c 25c 85c 125c 30 35 40 45 50 55 60 2.53 3.544.55 5.56 v dd [v] pull-up resistance [k ohm ] -40c 25c 85c 125c
stm8af61xx, stm8af62xx electrical characteristics doc id 14952 rev 6 61/89 figure 22. typical pull-up current i pu vs v dd @ four temperatures typical output level curves figure 23 to figure 32 show typical output level curves measured with output on a single pin. 0 20 40 60 80 100 120 140 0123456 v dd [v] pull-up current [a] -40c 25c 85c 125c note: the pull-up is a pure resistor (slope goes through 0). figure 23. typ. v ol @ v dd = 3.3 v (standard ports) figure 24. typ. v ol @ v dd = 5.0 v (standard ports) 0 0.25 0.5 0.75 1 1.25 1.5 01234567 i ol [ma] v ol [v] -40c 25c 85c 125c 0 0.25 0.5 0.75 1 1.25 1.5 024681012 i ol [ma] v ol [v] -40c 25c 85c 125c figure 25. typ. v ol @ v dd = 3.3 v (true open drain ports) figure 26. typ. v ol @ v dd = 5.0 v (true open drain ports) 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 02468101214 i ol [ma] v ol [v] -40c 25c 85c 125c 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 0 5 10 15 20 25 i ol [ma] v ol [v] -40c 25c 85c 125c
electrical characteristics stm8af61xx, stm8af62xx 62/89 doc id 14952 rev 6 figure 27. typ. v ol @ v dd = 3.3 v (high sink ports) figure 28. typ. v ol @ v dd = 5.0 v (high sink ports) 0 0.25 0.5 0.75 1 1.25 1.5 02468101214 i ol [ma] v ol [v] -40c 25c 85c 125c 0 0.25 0.5 0.75 1 1.25 1.5 0 5 10 15 20 25 i ol [ma] v ol [v] -40c 25c 85c 125c figure 29. typ. v dd - v oh @ v dd = 3.3 v (standard ports) figure 30. typ. v dd - v oh @ v dd = 5.0 v (standard ports) 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 01234567 i oh [ma] v dd - v oh [v] -40c 25c 85c 125c 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 024681012 i oh [ma] v dd - v oh [v] -40c 25c 85c 125c figure 31. typ. v dd - v oh @ v dd = 3.3 v (high sink ports) figure 32. typ. v dd - v oh @ v dd = 5.0 v (high sink ports) 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 02468101214 i oh [ma] v dd - v oh [v] -40c 25c 85c 125c 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 0 5 10 15 20 25 i oh [ma] v dd - v oh [v] -40c 25c 85c 125c
stm8af61xx, stm8af62xx electrical characteristics doc id 14952 rev 6 63/89 10.3.7 reset pin characteristics subject to general operating conditions for v dd and t a unless otherwise specified. figure 33. typical nrst v il and v ih vs v dd @ four temperatures table 38. nrst pin characteristics symbol parameter conditions min typ max unit v il(nrst) nrst input low level voltage (1) 1. data based on characterization results, not tested in production. - v ss - 0.3 x v dd v ih(nrst) nrst input high level voltage (1) - 0.7 x v dd - v dd v ol(nrst) nrst output low level voltage (1) i ol = 3 ma - - 0.6 v r pu(nrst) nrst pull-up resistor - 30 40 60 k t ifp nrst input filtered pulse (1) -85-315ns t ifp(nrst) nrst input not filtered pulse duration (2) 2. data guaranteed by design, not tested in production. 500 ns 0 1 2 3 4 5 6 2.5 3 3.5 4 4.5 5 5.5 6 v dd [v] v il / v ih [v] -40c 25c 85c 125c
electrical characteristics stm8af61xx, stm8af62xx 64/89 doc id 14952 rev 6 figure 34. typical nrst pull-up resistance r pu vs v dd figure 35. typical nrst pull-up current i pu vs v dd the reset network shown in figure 36 protects the device against parasitic resets. the user must ensure that the level on the nrst pin can go below v il(nrst) max (see ta b l e 38: nrst pin characteristics ), otherwise the reset is not taken into account internally. figure 36. recommended reset pin protection 30 35 40 45 50 55 60 2.5 3 3.5 4 4.5 5 5.5 6 v dd [v] nrst pull-up resistance [k ohm ] -40c 25c 85c 125c 0 20 40 60 80 100 120 140 0123456 v dd [v] nrst pull-up current [a] -40c 25c 85c 125c external reset circuit stm8a filter r pu v dd internal reset nrst 0.1f (optional)
stm8af61xx, stm8af62xx electrical characteristics doc id 14952 rev 6 65/89 10.3.8 tim 1, 2, 3, a nd 4 timer specifications subject to general operating conditions for v dd , f master , and t a unless otherwise specified. 10.3.9 spi serial peripheral interface unless otherwise specified, the parameters given in ta bl e 40 are derived from tests performed under ambient temperature, f master frequency and v dd supply voltage conditions. t master = 1/f master . refer to i/o port characteristics for more de tails on the input/output alternate function characteristics (nss , sck, mosi, miso). table 39. tim 1, 2, 3, and 4 electrical specifications symbol parameter conditions min typ max unit f ext timer external clock frequency (1) 1. not tested in production. on 64 kbyte de vices, the frequency is limited to 16 mhz. ---16mhz table 40. spi characteristics symbol parameter conditions min max unit f sck 1/t c(sck) spi clock frequency master mode 0 10 mhz slave mode v dd < 4.5 v 0 6 (1) v dd = 4.5 v to 5.5 v 0 8 (1) t r(sck ) t f(sck) spi clock rise and fall time capacitive load: c = 30 pf - 25 (2) ns t su(nss) (3) nss setup time slave mode 4 * t master - t h(nss) (3) nss hold time slave mode 70 - t w(sckh) (3) t w(sckl) (3) sck high and low time master mode t sck /2 - 15 t sck /2 + 15 t su(mi) (3) t su(si) (3) data input setup time master mode 5 - slave mode 5 - t h(mi) (3) t h(si) (3) data input hold time master mode 7 - slave mode 10 - t a(so) (3)(4) data output access time slave mode - 3* t master t dis(so) (3)(5) data output disable time slave mode 25 t v(so) (3) data output valid time slave mode (after enable edge) v dd < 4.5 v - 75 v dd = 4.5 v to 5.5 v - 53 t v(mo) (3) data output valid time master mode (after enable edge) - 30 t h(so) (3) data output hold time slave mode (after enable edge) 31 - t h(mo) (3) master mode (after enable edge) 12 - 1. f sck < f master /2. 2. the pad has to be configured accordingly (fast mode). 3. values based on design simulation and/or charac terization results, and not tested in production.
electrical characteristics stm8af61xx, stm8af62xx 66/89 doc id 14952 rev 6 figure 37. spi timing diagram where slave mode and cpha = 0 1. measurement points are at cmos levels: 0.3 v dd and 0.7 v dd . figure 38. spi timing diagram where slave mode and cpha = 1 1. measurement points are at cmos levels: 0.3 v dd and 0.7 v dd . 4. min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. 5. min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in hi-z. ai14134 sck input cpha= 0 mosi input miso out p ut cpha= 0 ms b o u t msb in bi t6 ou t lsb in lsb out cpol=0 cpol=1 bit1 in nss input t su(nss) t c(sck) t h(nss) t a(so) t w(sckh) t w(sckl) t v(so) t h(so) t r(sck) t f(sck) t dis(so) t su(si) t h(si) ai14135 sck input cpha=1 mosi input miso out p ut cpha=1 ms b o u t msb in bi t6 ou t lsb in lsb out cpol=0 cpol=1 bit1 in t su(nss) t c(sck) t h(nss) t a(so) t w(sckh) t w(sckl) t v(so) t h(so) t r(sck) t f(sck) t dis(so) t su(si) t h(si) nss input
stm8af61xx, stm8af62xx electrical characteristics doc id 14952 rev 6 67/89 figure 39. spi timing diagram - master mode 1. measurement points are at cmos levels: 0.3 v dd and 0.7 v dd . ai 3#+output #0(! -/3) /5454 -)3/ ).0 54 #0(! -3 "). - 3"/54 ") 4). ,3"/54 ,3"). #0/, #0/, " ) 4/54 .33input t c3#+ t w3#+( t w3#+, t r3#+ t f3#+ t h-) (igh 3#+output #0(! #0(! #0/, #0/, t su-) t v-/ t h-/
electrical characteristics stm8af61xx, stm8af62xx 68/89 doc id 14952 rev 6 10.3.10 i 2 c interface characteristics table 41. i 2 c characteristics symbol parameter standard mode i 2 c fast mode i 2 c (1) 1. f master , must be at least 8 mhz to achieve max fast i 2 c speed (400 khz) unit min (2) 2. data based on standard i 2 c protocol requirement, not tested in production max (2) min (2) max (2) t w(scll) scl clock low time 4.7 - 1.3 - s t w(sclh) scl clock high time 4.0 - 0.6 - t su(sda) sda setup time 250 - 100 - ns t h(sda) sda data hold time 0 (3) 3. the maximum hold time of the start condition has only to be met if the interface does not stretch the low time - 0 (4) 4. the device must internally provide a hold time of at least 300 ns for th e sda signal in order to bridge the undefined region of the falling edge of scl 900 (3) t r(sda) t r(scl) sda and scl rise time (v dd = 3 to 5.5 v) - 1000 - 300 t f(sda) t f(scl) sda and scl fall time (v dd = 3 to 5.5 v) - 300 - 300 t h(sta) start condition hold time 4.0 - 0.6 - s t su(sta) repeated start condition setup time 4.7 - 0.6 - t su(sto) stop condition setup time 4.0 - 0.6 - s t w(sto:sta) stop to start condition time (bus free) 4.7 - 1.3 - s c b capacitive load for each bus line - 400 - 400 pf
stm8af61xx, stm8af62xx electrical characteristics doc id 14952 rev 6 69/89 10.3.11 10-bit adc characteristics subject to general operating conditions for v dda , f master , and t a unless otherwise specified. figure 40. typical application with adc 1. legend: r ain = external resistance, c ain = capacitors, c samp = internal sample and hold capacitor. table 42. adc characteristics symbol parameter conditions min typ max unit f adc adc clock frequency - 111 khz - 4 mhz khz/mhz v dda analog supply - 3 - 5.5 v v ref+ positive reference voltage - 2.75 - v dda v ref- negative reference voltage - v ssa -0.5 v ain conversion voltage range (1) 1. during the sample time, the sampling capacitance, c samp (3 pf typ), can be charged/discharged by the external source. the internal resistance of the analog source must allow the capacitance to reach its final voltage level within t s. after the end of the sample time t s , changes of the analog input voltage have no effect on the conversion result. - v ssa - v dda devices with external v ref+ / v ref- pins v ref- - v ref+ c samp internal sample and hold capacitor - - - 3 pf t s (1) sampling time (3 x 1/f adc ) f adc = 2 mhz - 1.5 - s f adc = 4 mhz - 0.75 - t stab wakeup time from standby f adc = 2 mhz - 7 - f adc = 4 mhz - 3.5 - t conv total conversion time including sampling time (14 x 1/f adc ) f adc = 2 mhz - 7 - f adc = 4 mhz - 3.5 - r switch equivalent switch resistance - - - 30 k ainx stm8a v dd i l v t 0.6v v t 0.6v v ain r ain 10-bit a/d conversion c ain t s c samp rswitch
electrical characteristics stm8af61xx, stm8af62xx 70/89 doc id 14952 rev 6 figure 41. adc accura cy characteristics 1. example of an actual transfer curve 2. the ideal transfer curve 3. end point correlation line e t = total unadjusted error: maximum deviation betw een the actual and the ideal transfer curves. e o = offset error: deviation between the fi rst actual transition and the first ideal one. e g = gain error: deviation between the last ideal transition and the last actual one. e d = differential linearity error: maximum dev iation between actual steps and the ideal one. e l = integral linearity error: maximum deviation between any actual transition an d the end point correlation line. table 43. adc accuracy for v dda = 5 v symbol parameter conditions typ max (1) 1. max value is based on characte rization, not tested in production. unit |e t | total unadjusted error (2) 2. adc accuracy vs. injection current: any positive or negat ive injection current within the limits specified for i inj(pin) and i inj(pin) in section 10.3.6 does not affect the adc accuracy. f adc = 2 mhz 1.4 3 (3) 3. tue 2lsb can be reached on specific sale stypes on the whole temperature range. lsb |e o | offset error (2) 0.8 3 |e g | gain error (2) 0.1 2 |e d | differential linearity error (2) 0.9 1 |e l | integral linearity error (2) 0.7 1.5 |e t | total unadjusted error (2) f adc = 4 mhz 1.9 (4) 4. target values. 4 (4) |e o | offset error (2) 1.3 (4) 4 (4) |e g | gain error (2) 0.6 (4) 3 (4) |e d | differential linearity error (2) 1.5 (4) 2 (4) |e l | integral linearity error (2) 1.2 (4) 1.5 (4) e o e g 1lsb ideal 1lsb ideal v dda v ssa ? 1024 ---------------------------------------- - = 1023 1022 1021 5 4 3 2 1 0 7 6 1234567 1021102210231024 (1) (2) e t e d e l (3) v dda v ssa
stm8af61xx, stm8af62xx electrical characteristics doc id 14952 rev 6 71/89 10.3.12 emc characteristics susceptibility tests ar e performed on a sample basis du ring product ch aracterization. functional ems (electromagnetic susceptibility) while executing a simple application (toggling 2 leds through i/o ports), the product is stressed by two electromagnetic events unt il a failure occurs (indicated by the leds). esd : electrostatic discharge (positive and negati ve) is applied on all pins of the device until a functional disturbance occurs. this test conforms with the iec 1000-4-2 standard. ftb : a burst of fast transient voltage (positive and negative) is applied to v dd and v ss through a 100 pf capacitor, until a function al disturbance occurs. this test conforms with the iec 1000-4-4 standard. a device reset allows normal operations to be resumed. the test results are given in the table below based on the ems levels and classes defined in application note an1709. designing hardened software to avoid noise problems emc characterization and optimization are per formed at component level with a typical application environment and simplified mcu software. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the us er applies emc software optimization and prequalification tests in relation with the emc level requested for his application. software recommendations the software flowchart must include the management of runaway conditions such as: corrupted program counter unexpected reset critical data corruption (control registers...) prequalification trials most of the common failures (unexpected reset and program counter corruption) can be recovered by applying a low state on the nr st pin or the oscilla tor pins for 1 second. to complete these trials, esd stress can be app lied directly on the device, over the range of specification values. when unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note an1015). table 44. ems data symbol parameter conditions level/class v fesd voltage limits to be applied on any i/o pin to induce a functional disturbance v dd = 3.3 v, t a = 25 c, f master = 16 mhz (hsi clock), conforms to iec 1000-4-2 3b v eftb fast transient voltage burst limits to be applied through 100 pf on v dd and v ss pins to induce a functional disturbance v dd = 3.3 v, t a = 25 c, f master = 16 mhz (hsi clock), conforms to iec 1000-4-4 4a
electrical characteristics stm8af61xx, stm8af62xx 72/89 doc id 14952 rev 6 electromagnetic interference (emi) emission tests conform to the sae j 1752/3 stan dard for test software , board layout and pin loading. absolute maximum ratings (electrical sensitivity) based on two different tests (esd and lu) using specific measurement methods, the product is stressed to determine its performance in terms of electrical sensitivity. for more details, refer to the ap plication note an1181. electrostatic discharge (esd) electrostatic discharges (3 positive then 3 n egative pulses separated by 1 second) are applied to the pins of each sample according to each pin combination. the sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). this test conforms to the jesd22-a114a/a115a standard. for more details, refer to the application note an1181. table 45. emi data symbol parameter conditions unit general conditions monitored frequency band max f cpu (1) 1. data based on characterization results, not tested in production. 8 mhz 16 mhz s emi peak level v dd = 5 v, t a = 25 c, lqfp80 package conforming to sae j 1752/3 0.1 mhz to 30 mhz 15 17 dbv 30 mhz to 130 mhz 18 22 130 mhz to 1 ghz -1 3 sae emi level ? 2 2.5 table 46. esd absolute maximum ratings symbol ratings conditions class maximum value (1) 1. data based on characterization results, not tested in production unit v esd(hbm) electrostatic discharge voltage (human body model) t a = 25c, conforming to jesd22-a114 3a 4000 v v esd(cdm) electrostatic discharge voltage (charge device model) t a = 25c, conforming to jesd22-c101 3 500 v esd(mm) electrostatic discharge voltage (machine model) t a = 25c, conforming to jesd22-a115 b 200
stm8af61xx, stm8af62xx electrical characteristics doc id 14952 rev 6 73/89 static latch-up two complementary static tests are required on 10 parts to assess the latch-up performance. a supply overvoltage (applied to each power supply pin) and a current injection (applied to each input, output and configurable i/o pin) are performed on each sample. this test conforms to the eia/jesd 78 ic la tch-up standard. for more details, refer to the application note an1181. 10.4 thermal characteristics in case the maximum chip junction temperature (t jmax ) specified in ta bl e 23: general operating conditions on page 49 is exceeded, the functionality of the device cannot be guaranteed. t jmax , in degrees celsius, may be calculated using the following equation: t jmax = t amax + (p dmax x ja ) where: ?t amax is the maximum ambient temperature in c ? ja is the package junction-to-ambient thermal resistance in c/w ?p dmax is the sum of p intmax and p i/omax (p dmax = p intmax + p i/omax ) ?p intmax is the product of i dd and v dd , expressed in watts. this is the maximum chip internal power. ?p i/omax represents the maximum power dissipation on output pins where: p i/omax = (v ol *i ol ) + ((v dd -v oh )*i oh ), taking into account the actual v ol /i ol and v oh /i oh of the i/os at low and high level in the application. table 47. electrical sensitivities symbol parameter conditions class (1) 1. class description: a class is an stmi croelectronics internal specification. all its limits are higher than the jedec specifications, that means when a device belongs to class a it exceeds the jedec standard. b class strictly covers all the jedec criteria (international standard). lu static latch-up class t a = 25 c a t a = 85 c t a = 125 c t a = 150 c (2) 2. available on stm8af62xx devices only.
electrical characteristics stm8af61xx, stm8af62xx 74/89 doc id 14952 rev 6 10.4.1 reference document jesd51-2 integrated circuits thermal test method environment conditions - natural convection (still air). available from www.jedec.org. 10.4.2 selecting the pro duct temperature range when ordering the microcontroller, the temper ature range is specified in the order code (see section 12: ordering information ). the following example shows how to calculate the temperature range needed for a given application. assuming the following application conditions: maximum ambient temperature t amax = 82 c (measured according to jesd51-2), i ddmax = 14 ma, v dd = 5 v, maximum 20 i/os used at the same time in output at low level with i ol = 8 ma, v ol = 0.4 v p intmax = 14 ma x 5 v= 70 mw p iomax = 20 x 8 ma x 0.4 v = 64 mw this gives: p intmax = 70 mw and p iomax 64 mw: p dmax = 70 mw + 64 mw thus: p dmax = 134 mw. using the values obtained in ta b l e 48: thermal characteristics on page 74 t jmax is calculated as follows: for lqfp64 46 c/w t jmax = 82 c + (46 c/w x 134 mw) = 82 c + 6 c = 88 c this is within the range of the suffix b version parts (-40 < t j < 105 c). parts must be ordered at least with the temperature range suffix b. table 48. thermal characteristics (1) 1. thermal resistances are based on jedec jesd51- 2 with 4-layer pcb in a natural convection environment. symbol parameter value unit ja thermal resistance junction-ambient lqfp 48 - 7 x 7 mm 57 c/w ja thermal resistance junction-ambient lqfp 32 - 7 x 7 mm 59 c/w ja thermal resistance junction-ambient vfqfpn32 25 c/w
stm8af61xx, stm8af62xx package characteristics doc id 14952 rev 6 75/89 11 package characteristics in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark.
package characteristics stm8af61xx, stm8af62xx 76/89 doc id 14952 rev 6 11.1 package mechanical data figure 42. vfqfpn 32-lead very thin fine pitch quad flat no-lead package (5 x 5) table 49. vfqfpn 32-lead very thin fine pitch quad flat no-lead package mechanical data dim. mm inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits min typ max min typ max a 0.800 0.900 1.000 0.0315 0.0354 0.0394 a1 0.000 0.020 0.050 0.000 0.0008 0.0020 a3 ? 0.200 ? ? 0.0079 ? b 0.180 0.250 0.300 0.0071 0.0098 0.0118 d 4.850 5.000 5.150 0.1909 0.1969 0.2028 d2 3.400 3.450 3.500 0.1339 0.1358 0.1378 e 4.850 5.000 5.150 0.1909 0.1969 0.2028 e2 3.400 3.450 3.500 0.1339 0.1358 0.1378 e ? 0.500 ? ? 0.0197 ? l 0.300 0.400 0.500 0.0118 0.0157 0.0197 ddd ? ? 0.080 ? ? 0.0031 seating plane ddd c c a3 a1 a d e 9 16 17 24 32 pin # 1 id r = 0.30 8 e l l d2 1 b e2 42_me bottom view
stm8af61xx, stm8af62xx package characteristics doc id 14952 rev 6 77/89 figure 43. lqfp 48-pin low profile quad flat package (7 x 7) 5b_me l a1 k l1 c a a2 ccc c d d1 d3 e3 e1 e 24 25 36 37 b 48 1 pin 1 identification 12 13 table 50. lqfp 48-pin low profile quad flat package mechanical data dim. mm inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits min typ max min typ max a ? ? 1.600 ? ? 0.0630 a1 0.050 ? 0.150 0.0020 ? 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 ? 0.200 0.0035 ? 0.0079 d 8.800 9.000 9.200 0.3465 0.3543 0.3622 d1 6.800 7.000 7.200 0.2677 0.2756 0.2835 d3 ? 5.500 ? ? 0.2165 ? e 8.800 9.000 9.200 0.3465 0.3543 0.3622 e1 6.800 7.000 7.200 0.2677 0.2756 0.2835 e3 ? 5.500 ? ? 0.2165 ? e ? 0.500 ? ? 0.0197 ? 0 3.5 7 0 3.5 7 l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 ? 1.000 ? ? 0.0394 ? ccc ? ? 0.080 ? ? 0.0031
package characteristics stm8af61xx, stm8af62xx 78/89 doc id 14952 rev 6 figure 44. lqfp 48-pin recommended footprint 1. drawing is not to scale. dime nsions are in millimeters. "?&0
stm8af61xx, stm8af62xx package characteristics doc id 14952 rev 6 79/89 figure 45. lqfp 32-pin low profile quad flat package (7 x 7) table 51. lqfp 32-pin low profile quad flat package mechanical data dim. mm inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits min typ max min typ max a ? ? 1.600 ? ? 0.0630 a1 0.050 ? 0.150 0.0020 ? 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.300 0.370 0.450 0.0118 0.0146 0.0177 c 0.090 ? 0.200 0.0035 ? 0.0079 d 8.800 9.000 9.200 0.3465 0.3543 0.3622 d1 6.800 7.000 7.200 0.2677 0.2756 0.2835 d3 ? 5.600 ? ? 0.2205 ? e 8.800 9.000 9.200 0.3465 0.3543 0.3622 e1 6.800 7.000 7.200 0.2677 0.2756 0.2835 e3 ? 5.600 ? ? 0.2205 ? e ? 0.800 ? ? 0.0315 ? 0 3.5 7 0 3.5 7 l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 ? 1.000 ? ? 0.0394 ? ccc ? ? 0.100 ? ? 0.0039 5v_me l a1 k l1 c a a2 ccc c d d1 d3 e3 e1 e 16 17 24 25 b 32 1 pin 1 identification 8 9
package characteristics stm8af61xx, stm8af62xx 80/89 doc id 14952 rev 6 figure 46. lqfp 32-pin recommended footprint 1. drawing is not to scale. dime nsions are in millimeters. 6?&0
stm8af61xx, stm8af62xx ordering information doc id 14952 rev 6 81/89 12 ordering information figure 47. ordering information scheme (1) 1. for a list of available options (e.g. memory size, package) and or derable part numbers or for further information on any aspect of this device, please go to www.st.com or contact the st sales office nearest to you. 2. customer specific fastrom code or custom device configuration. this field shows ?sss? if the device contains a super set silicon, usua lly equipped with bigger memory and mo re i/os. this silicon is supposed to be replaced later by the target silicon. 3. not recommended for new design. 4. available on stm8af62xx devices. stm8a f 62 6 8 t d xxx (2) y product class 8-bit automotive microcontroller program memory size 2 = 8 kbytes 4 = 16 kbytes 6 = 32 kbytes package type t = lqfp u = vfqfpn example: device family 61 = silicon rev y, lin only (3) 62 = silicon rev x and rev w, lin only program memory type f = flash + eeprom p= fastrom h = flash no eeprom (3) temperature range a = -40 to 85 c b = -40 to 105 c (3) c = -40 to 125 c d = -40 to 150 c (4) pin count 6 = 32 pins 8 = 48 pins packing y = tray u = tube x = tape and reel compliant with eia 481-c
stm8 development tools stm8af61xx, stm8af62xx 82/89 doc id 14952 rev 6 13 stm8 development tools development tools for the stm8a microcontrollers include the stice emulation system offeri ng tracing and code profiling stvd high-level language debugger including assembler and visual development environment - seamless integration of third party c compilers. stvp flash programming software in addition, the stm8a comes with starter ki ts, evaluation boards and low-cost in-circuit debugging/programming tools. 13.1 emulation and in-circuit debugging tools the stm8 tool line includes the stice emulation system offering a complete range of emulation and in-circuit debugging features on a platform that is designed for versatility and cost-effectiveness. in addition, stm8a applicat ion development is supported by a low-cost in-circuit debugger/programmer. the stice is the fourth generation of full-featured emulators from stmicroelectronics. it offers new advanced debuggin g capabilities including tracing, profiling and code coverage analysis to help detect execution bottlenecks and dead code. in addition, stice offers in-circuit debugging and programming of stm8a microcontrollers via the stm8 single wire interface module (swim), which allows non-intrusive debugging of an application while it runs on the target microcontroller. for improved cost effectiveness, stice is based on a modular design that allows you to order exactly what you need to meet your development requirements and to adapt your emulation system to support existing and future st microcontrollers. 13.1.1 stice key features program and data trace recording up to 128 k records advanced breakpoints with up to 4 levels of conditions data breakpoints real-time read/write of all device resources during emulation occurrence and time profiling and code coverage analysis (new features) in-circuit debugging/programming via swim protocol 8-bit probe analyzer 1 input and 2 output triggers usb 2.0 high speed interface to host pc power supply follower managing application voltages between 1.62 to 5.5 v modularity that allows you to specify the components you need to meet your development requirements and adapt to future requirements. supported by free software tools that include integrated development environment (ide), programming software interface and assembler for stm8.
stm8af61xx, stm8af62xx stm8 development tools doc id 14952 rev 6 83/89 13.2 software tools stm8 development tools are supported by a complete, free software package from stmicroelectronics that includes st vis ual develop (stvd) ide and the st visual programmer (stvp) software interface. stvd provides seamless integration of the cosmic and raisonance c compilers for stm8. 13.2.1 stm8 toolset the stm8 toolset with stvd integrated development environment and stvp programming software is available for free download at www.st.com. this package includes: st visual develop full-featured integrated development environment from stmicroelectronics, featuring: seamless integration of c and asm toolsets full-featured debugger project management syntax highlighting editor integrated programming interface support of advanced emulati on features for stice such as code profiling and coverage st visual programmer (stvp) easy-to-use, unlimited graphical interface allowing read, write and verification of the stm8a microcontroller?s flash memory. stvp also offers project mode for saving programming configurations and automating programming sequences. 13.2.2 c and assembly toolchains control of c and assembly toolchains is seam lessly integrated into the stvd integrated development environment, making it possible to configure and control the building of your application directly from an easy-to-use graphical interface. available toolchains include: c compiler for stm8 all compilers are available in free version with a limited code size depending on the compiler. for more informatio n, refer to www.cosmic-software.com, www.raisonance.com, and www.iar.com. stm8 assembler linker free assembly toolchain included in the stm8 toolset, which allows you to assemble and link your applicat ion source code.
stm8 development tools stm8af61xx, stm8af62xx 84/89 doc id 14952 rev 6 13.3 programming tools during the development cycle, stice provides in-circuit programming of the stm8a flash microcontroller on your application board via the swim protocol. additional tools are to include a low-cost in-circuit programmer as well as st socket boards, which provide dedicated programming platforms with sockets for programming your stm8a. for production environments, programmers w ill include a complete range of gang and automated programming solutions from third-party tool developers already supplying programmers for the stm8 family.
stm8af61xx, stm8af62xx revision history doc id 14952 rev 6 85/89 14 revision history table 52. document revision history date revision changes 22-aug-2008 1 initial release 10-aug-2009 2 document revised as the following: updated features on page 1 ; updated table 1: device summary ; updated section 3: product line-up ; changed section 5: product overview ; updated section 6: pinouts and pin description ; changed section 7.2: register map ; updated section 8: interrupt table ; updated section 9: option bytes ; updated section 10: electrical characteristics ; updated section 11: package characteristics ; updated section 12: ordering information ; added section 13: stm8 development tools . 22-oct-2009 3 adapted table 10: stm8af61xx/62xx (32 kbytes) microcontroller pin description . added section 13.4.5: lin header error when automatic resynchronization is enabled . 08-jul-2010 4 updated title on cover page. added vfqfpn32 5x 5 mm package. added stm8af62xx devices, and modified cover page header to clarify the part numbers cover ed by the datasheets. updated note 1 below table 1: device summary. updated d temperature range to -40 to 150c. content of section 5: product overview reorganized. renamed section 7 memory and register map , and content merged with register map section. renamed bl_en and nbl_en, bl and nbl, respectively, in table 17: option bytes . added table 22: operating lifetime . added cext and p d (power dissipation) in table 23: general operating conditions , and section 10.3.1: vcap external capacitor . suffix d maximum junction temperature (t j ) updated in table 23: general operating conditions . update t vdd in table 24: operating conditions at power-up/power- down . moved table 29: typical peripheral current consumption vdd = 5.0 v to section : current consumption for on-chip peripherals and removed i dd(can) . updated section 12: ordering information for the devices supported by the datasheet. updated section 13: stm8 development tools .
revision history stm8af61xx, stm8af62xx 86/89 doc id 14952 rev 6 31-jan-2011 5 modified references to reference manual, and flash programming manual in the whole document. added reference to aec q100 standard on cover page. renamed timer types as follows: ? auto-reload timer to general purpose timer ? multipurpose timer to advanced control timer ? system timer to basic timer introduced concept of medium density flash program memory. updated timer names in figure 1: stm8a block diagram . added tmu brief description in section 5.4: flash program and data eeprom , and updated tmu_maxatt description in table 18: option byte description . updated clock sources in clock controller features ( section 5.5.1 ). changed 16mhztrim0 to hsitrim bit in section : user trimming . added table 4: peripheral clock gating bits in section 5.5.6 . updated section 5.6: low-power operating modes . added calibration using tim3 in section 5.7.2: auto-wakeup counter . added table 7: adc naming and table 8: communication peripheral naming correspondence . added note 1 related ain12 pin in section 5.8: analog-to-digital converter (adc) and table 10: stm8af61xx/62xx (32 kbytes) microcontroller pin description . updated spi data rate to 10 mbit/s or f master /2 in section 5.9.1: serial peripheral interface (spi) . added reset state in table 9: legend/abbreviation . table 10: stm8af61xx/62xx (32 kbytes) microcontroller pin description : added note 7 related to pd1/swim, modified note 6 , corrected wpu input for pe1 and pe2, and renamed timn_ccx and timn_nccx to timn_chx and timn_chxn, respectively. section 7.2: register map : replaced tables describing register maps and reset values for non- volatile memory, global configurati on, reset status, clock controller, interrupt controller, timers, communication interfaces, and adc, by table 13: general hardware register map . added note 1 for px_idr registers in table 12: i/o port hardware register map . updated register reset values for px_idr registers. added swim and debug module register map. table 52. document revision history (continued) date revision changes
stm8af61xx, stm8af62xx revision history doc id 14952 rev 6 87/89 31-jan-2011 5 (continued) renamed fast active halt mode to active-halt mode with regulator on, and slow active halt mode to active-halt mode with regulator off. updated table 26: total current consumption in halt and active-halt modes. general conditions for vdd apply, ta = -40 to 55 c , in particular i dd(fah) and i dd(sah) renamed i dd(ah) ; t wu(fah) and t wu(sah) renamed t wu(ah) , and temperature condition added. removed i dd(usart) from table 29: typical peripheral current consumption vdd = 5.0 v . updated general conditions in section 10.3.5: memory characteristics . modified t we maximum value in table 35: flash program memory and table 36: data memory . update i lkg ana maximum value for t a ranging from ? 40 to 150 c in table 37: i/o static characteristics . added t ifp(nrst) and renamed v f(nrst) t ifp in table 38: nrst pin characteristics . added recommendations concerning nrst pin level above figure 36: recommended reset pin protection , and updated external capacitor value. added raisonance compiler in section 13.2: software tools . moved know limitations to separate errata sheet. 18-jul-2012 6 updated wildcards of document part numbers. table 1: device summary : updated footnote 1 and added footnote 2 to all stm8af61xx part numbers. section 1: introduction : small text change in first paragraph. table 2: stm8af62xx product line-up : added ?p? version for all order codes; updated ram. table 3: stm8af/h61xx product line-up : added ?p? version for all order codes. figure 1: stm8a block diagram : updated por, bor and wdg; updated linuart input; added legend. section 5.4: flash program and data eeprom : removed nonrelevant bullet points and added a sentence about the factory programme. table 4: peripheral clock gating bit assignments in clk_pckenr1/2 registers : updated adc features : updated adc input range. table 11: memory model for the devices covered in this datasheet : updated 16 kbyte and 8 kbyte information. table 17: option bytes : updated factory default setting for nopt17; added footnote 1 . section 10.1.1: minimum and maximum values : t a = -40 c (not 40 c). table 23: general operating conditions : updated v cap . table 25: total current consumption in run, wait and slow mode. general conditions for vdd apply, ta = -40 to 150 c : updated conditions for i dd(run) . table 37: i/o static characteristics : added new condition and new max values for rise and fall time; updated footnote 2 . table 52. document revision history (continued) date revision changes
revision history stm8af61xx, stm8af62xx 88/89 doc id 14952 rev 6 18-jul-2012 6 (continued) section 10.3.7: reset pin characteristics : updated text below figure 35: typical nrst pull-up current ipu vs vdd . figure 36: recommended reset pin protection : updated unit of capacitor. table 40: spi characteristics : updated sck high and low time conditions and values. figure 39: spi timing diagram - master mode : replaced ?sck input? signals with ?sck output? signals. updated table 49: vfqfpn 32-lead very thin fine pitch quad flat no- lead package mechanical data , table 50: lqfp 48-pin low profile quad flat package mechanical data , and table 51: lqfp 32-pin low profile quad flat package mechanical data . replaced figure 43: lqfp 48-pin low profile quad flat package (7 x 7) and figure 45: lqfp 32-pin low profile quad flat package (7 x 7) . added figure 44: lqfp 48-pin recommended footprint and figure 46: lqfp 32-pin recommended footprint . figure 47: ordering information scheme(1) : added footnote 1 , added ?xxx? and footnote 2 , updated example and device family; added fastrom. section 13.2.2: c and assembly toolchains : added www.iar.com table 52. document revision history (continued) date revision changes
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